memory-design

Design of 6T, 8T and 10T SRAM Cells with Static Noise Margin Analysis

Python tools for generating and testing SPICE netlists/waveforms involving crossbar memory arrays in various configurations

This project implements a single-port RAM using Verilog. The design simulates a memory module with a single read/write port, supporting basic memory operations like data storage and retrieval. It includes testbenches for functional verification and timing analysis to ensure reliable operation.

Design and analysis of a 7T SRAM cell using Cadence Virtuoso in 90 nm CMOS technology.

This repository contains a Verilog-based design and testbench for modeling a simple asynchronous RAM module. It is designed to simulate basic memory read/write behavior without the use of a clock, allowing learners and engineers to better understand low-level memory interactions.

Behavioral architecture of a read/write cycle controller for a DRAM chip.

Complete 64-bit 6T SRAM array with custom peripheral circuits in 120nm PDK. Achieved 3× FOM improvement through VDD/2 precharge and OTA-based sense amplifiers.

Repository with shell scripts, OS installation tasks, assembly language, and HDL files for the Computer Architecture and Operating Systems (ACSO) course at Escuela Colombiana de Ingeniería.

6T SRAM cell and 2x2 array with reproducible read/write/retention simulations and measured results.

PESU Sem 3: Mini project for Digital Design and Computer Organization

Parameterized Single-Port RAM Design and Verification using Verilog HDL

An Associative Memory Cache (AMC) design implemented and simulated using Digital logic simulator. This design demonstrates associative cache concepts including content-based address matching, tag comparison, hit/miss detection, and memory access control using digital circuit design.

Parameterized Dual-Port RAM Design and Verification using Verilog HDL

An asynchronous fifo keeps two independent clocks: one for writing and one for reading.

Implemented and verified synchronous RAM, asynchronous RAM, and ROM modules in Verilog HDL, covering core memory read/write behavior and timing, each validated with a dedicated testbench.

Parameterized single-port and dual-port memory subsystem with arbitration, verification, and FPGA-ready RTL implementation.

7T SRAM bit-cell in Cadence Virtuoso (gpdk090 90nm) — schematic, layout, DRC/LVS clean, SNM and power characterization

SRAM Collection – Parameterized Verilog Modules for Single Port SRAM (sync/async read), Pseudo Dual Port SRAM (sync read), and True Dual Port SRAM – all parameterized, fully synthesizable, and demo’d with testbenches and waveforms.

Transistor-level design and physical layout of a 32 x 12-bit 6T SRAM macro in 65 nm CMOS.