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michaelcolby-git/README.md

Michael Colby — Electrical Engineering

Michael Colby

Electrical Engineering · Stony Brook University · B.E. expected May 2028
GPA: 3.92 / 4.00

I’m interested in digital hardware, CMOS circuits, memory, and embedded systems. This portfolio connects inspectable source code with repeatable verification, documented engineering choices, and measured simulation results.

Selected projects

Project Engineering focus Verification
32-bit Pipelined RISC Processor Five-stage datapath, forwarding, hazards, and branch control 26 scenarios; 3,000 randomized instructions
CMOS 8-bit ALU Transistor gates, ripple carry, and timing/power characterization 524,288 RTL vectors; 192 CMOS vectors
6T SRAM Cell & Array Differential bitlines, wordline control, read/write/hold operation 128 state checks; 32 read-differential checks

Each repository includes its design, executable checks, measured results, and implementation provenance.

Hardware experience

SEDS Rocket Avionics · University at Buffalo
Sensor-interface circuitry, microcontroller firmware, telemetry, circuit simulation, and integrated hardware debugging.

Space Bulls Rover · University at Buffalo
Sensor-interface and power-distribution PCBs, regulation and signal-conditioning simulation, board bring-up, and subsystem validation.

Technical background

Area Tools & languages
Digital design & verification Verilog, ModelSim, digital logic, pipelining
Circuits & EDA Cadence Virtuoso, SPICE, LTspice, ngspice, Altium, KiCad
Software & analysis C, C++, Python, MATLAB, Git
Laboratory Oscilloscopes, function generators, logic analyzers, microcontrollers

LinkedIn · Email

Pinned Loading

  1. risc32-pipeline risc32-pipeline Public

    Five-stage educational 32-bit Verilog pipeline with forwarding, load-use interlocks, and differential verification.

    Python

  2. cmos-8bit-alu cmos-8bit-alu Public

    8-bit static CMOS ALU with exhaustive RTL verification, transistor simulation, and measured timing/power.

    Python

  3. sram-6t-array sram-6t-array Public

    6T SRAM cell and 2x2 array with reproducible read/write/retention simulations and measured results.

    Python