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kyakyosharon / ripes-projects

🖥️ Explore 20 hands-on experiments to master RISC-V computer architecture concepts using the Ripes simulator for effective learning.

machine-learning computer-vision deep-learning image-processing pandas feature-extraction neural-networks performance-analysis riscv32 cache-memory fruit-detection freshness-detection assembly-programming tobaco-classification mango-classification processor-simulation ripes educational-labs

Updated Oct 1, 2026
Assembly

AleksaMCode / cache-simulator

Star

Trace-driven cache memory simulator with LRU, MRU, RR and Belady replacement policies.

simulator cache lru cache-storage lru-cache cache-simulator mru cache-replacement mru-cache most-recently-used cache-memory least-recently-used belady cache-simulation

Updated Dec 22, 2023
C#

marcotulio956 / cache.coherencyLAOCII

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Exerting coherency between caches with protocols in a Memory-Shared Multiprocessors system whether it has uniform memory access(UMA, symmetric) or not(non-UMA).

cache verilog computer-architecture memory-hierarchy computer-organization multiprocessor cache-memory coherence-protocol

Updated Mar 6, 2026
Verilog

EvilConundrum / mastering-csarch2

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Resources for CSARCH2 (Computer Organization and Architecture 2) to help students prepare for exams and build a strong foundation in computer architecture.

unicode ascii floating-point ieee-754 computer-architecture microprogramming number-systems cache-memory

Updated Sep 22, 2025

jeffotoni / gocache

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GoCache – High-Performance In-Memory Cache for Go

go golang memory cache-memory gocache

Updated Nov 21, 2025
Go

microup / vcache

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"vcache" is a library that provides a concurrent-safe in-memory cache to store key-value pairs.

go golang performance cache eviction cache-memory

Updated Aug 9, 2023
Go

chiissuu / MegatronixOS

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c simulator operating-systems systems-programming cache-memory

Updated Sep 9, 2026
C

Sarvagya-24-chaturvedi / Cache-Memory-Simulator

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CacheMap is a full-stack CPU cache simulator combining Python, Verilog, and DevOps with Docker, GitHub Actions, Nginx, Pytest, Prometheus, and Grafana.

python docker nginx flask devops docker-compose grafana prometheus ci-cd pytest verilog computer-architecture cache-simulator cache-memory github-actions

Updated Sep 13, 2026
Python

JustineBijuPaul / ripes-projects

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A curated collection of RISC-V assembly experiments for the Ripes simulator — the repository provides ready-to-run labs that illustrate key CPU design and performance concepts. Each experiment comes with explained theory, .asm code, and expected metrics, making it ideal as a learning resource or teaching toolkit.

riscv performance-analysis computer-architecture risc-v risc-processor riscv32 cache-memory assembly-programming processor-simulation ripes cpu-pipeline educational-labs

Updated Dec 6, 2025
Assembly

ridash2005 / Hierarchical-Cache-Design

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A modular and fully synthesizable 3-level (L1/L2/L3) cache memory subsystem implemented in SystemVerilog, featuring split L1 caches, a centralized L2, and a Last-Level L3 cache with coherence support.

asic fpga verilog vivado systemverilog computer-architecture memory-hierarchy cache-memory hardware-design rtl-design-and-verification

Updated May 14, 2026
SystemVerilog

Vicky-Christofilopoulou / Cache-Memory

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The task is to design a "family" of three microprocessors that differ in performance and cost for the same computational task, as a project in "Computer Architecture 2" course.

assembly performance-metrics matrix-multiplication memory-hierarchy cache-memory

Updated Jan 15, 2025
Assembly

aniketsingh03 / CacheMemory

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This project is an implementation of cache memory with load and store instructions in Verilog.

c verilog-hdl cache-memory

Updated Nov 4, 2017
C

soumyadeepdutta0205-sudo / configurable-cache-memory-subsystem

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Configurable Cache Memory Subsystem with Complete RTL-to-GDSII Implementation using OpenROAD.

asic verilog computer-architecture vlsi yosys semiconductor digital-design gdsii cache-memory physical-design openroad rtl-design rtl-to-gdsii

Updated Jul 3, 2026
Verilog

ArpitAswal / Global-News

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Global News is designed to provide users with easy access to global news in a seamless and user-friendly manner. The app focuses on delivering a smooth user experience while ensuring that users can easily find and read news articles relevant to their interests and location.

dart mvc-architecture location-services lazy-loading flutter voice-assistant api-integration gemini-api cache-memory getx-state-management