test-bench

High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model

Test bench to measure and investigate performance of Apache Maven project

A DAQ framework to enable complex measurement scenarios.

LIN (Local Interconnect Network) bus protocol, a serial communication protocol for automotive applications.

This example .BMP generator and ASCII script file reader can be adapted to test code such as pixel drawing algorithms, picture filters, and make use of a source ascii file to drive the inputs of your .sv DUT module while offering logging of the results, and executing the list of commands in order.

The Puppet Master for Embedded Target Boards: Dual-CDC USB test harness with MicroPython REPL & UART streaming bridge

Hardware-in-the-Loop (HIL) automation gateway and FastMCP server for embedded target boards

Implementation of a Parameterized Parallel Multiplier using Carry Save Adder in SystemVerilog and Xilinx Vivado.

Hardware and software for a BLDC thrust and torque measurement system using STM32.

Camera preview and test bench GUI for Raspberry Pi. Easy-install kiosk viewfinder for Kurokesu and other MIPI CSI camera modules (AR0234, AR0822, IMX283, IMX462, IMX477, IMX585, OS08E10), built on libcamera / picamera2

This repository contains Verilog HDL implementations of Half Adders, Full Adders, and 4-bit Adders, designed at three different abstraction levels: Gate Level, Dataflow Level, and Behavioral Level. These designs are fundamental to digital electronics, and this project showcases the versatility of Verilog in modeling and simulating digital circuits.

Laboratory test bench for testing and evaluating high-voltage semiconductor components and materials. Features a custom 12V-to-100V Boost converter, thermal simulations, and 3D-printed enclosure.

A slim PyQt5 Python desktop tool for real-time visualization and CSV/XLSX logging of GSV-6 / GSV-8 CAN measurement amplifiers using a dynamic device-channel tree view.

Banc de Mesure Botafumeiro - Excitation Paramétrique d'un Pendule

Designed, simulated, 3D-printed, and experimentally tested a manually variable-pitch propeller system — from blade theory and CAD through CFD validation to a self-built RPM and thrust measurement rig.

This repository contains a Verilog-based design and testbench for modeling a simple asynchronous RAM module. It is designed to simulate basic memory read/write behavior without the use of a clock, allowing learners and engineers to better understand low-level memory interactions.

VLSI System Design Practice Lab

Wireless ESP32-S3 test bench: control pins, PWM, servos, a live scope and I2C tools from your browser

Hosting all of my ZeroBraine Lua projects

Test bench commissioning web app: role-based dashboards, dependency-aware prioritised notifications, click-to-act task forms. FastAPI, PostgreSQL, Docker. Includes the original n8n prototype.