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J616s: USB4/Thunderbolt on the left back port (T6040 ACIO0) - #1220
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Teach the Apple USB4 glue and the PCIe-C controller the T6040 (M4 Pro) generation: the v2 router layout, its Type 7 NHI and the T6040 PCIe-C register and shared-MSI data. Taken from the driver half of the draft in linux#1052; the device tree half is already in integration. Tested on the J616s (M4 Pro) against the M2 over a TB5 cable: router firmware ready, XDomain link 2 x 20 Gb/s each way, thunderbolt-net iperf3 17.9 / 19.6 Gbit/s. Assisted-by: LLM Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com>
Take the lanes for USB4 or the Thunderbolt alternate mode: the common tunables and the CIO ones, the crossbar with orientation in one bit, both lanes released, then the same PHY firmware as USB3. USB3 stays parked until the lanes come back. The order is AppleT6040TypeCPhy mode 2 from the 25G83 kernelcache and matches the T6050 recipe, except for the AHB clock request at CFG +0x28. Not run on hardware. Signed-off-by: AxxzyWasTaken <axxzytte@gmail.com> (cherry picked from commit cf72776, linux#1126) Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com>
The T6040 (M4 Pro/Max) routers are reset through the PMGR CIO reconfig register, like T6000, and drive an LSTX sideband pin, like T8132. Add the apple,t6041-cio-reset compatible and let apple,t6040-usb4-acio carry the lstx pinctrl state and lstx-gpios. Assisted-by: LLM Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com>
… pins and Type-C ports Give each T6040 router its CIO reconfig reset line (ADT pmgr reg[44], enableCioReconfig at +0x2024), its LSTX pin and lstx-gpios (ADT acioN gpio-lstx: AOP pins 49, 51, 53), and label the routers' graph endpoints. The CIO reconfig block uses the T8132 PMGR compatibles. On the J614s/J616s link each Type-C connector to the router behind the same ATC PHY (ADT acioN atc-phy-parent): typec0 (left back) to ACIO0, typec1 (left front) to ACIO1, typec2 (right) to ACIO2. The port controller skips a link to a disabled router. Name the routers' aliases usb4-N-acio, the name the loader looks up for the router (RC) tuning, as on T8112. Nothing is enabled here. From linux#1165. Assisted-by: LLM Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com>
Enable ACIO0 (typec0, left back), its DART, NHI, mailbox, CIO reconfig block and power domains. The loader hands over the router, adapter and NHI tuning and the DROM. Give the router DART the ADT vm-base window so the NHI rings sit where its 32-bit + 1 TiB addressing reaches them. The PCIe tunnel stays off: host-to-host (XDomain, thunderbolt-net) and USB4 links only for now. Tested on the J616s against the M2 (TB5 cable): link after cold boot, 2 x 20 Gb/s each way, thunderbolt-net iperf3; see the PR for numbers. Assisted-by: LLM Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com>
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Hardware proof on the J616s (M4 Pro), cabled to the M2 with a TB5 cable. The test kernel 7.3.0-aurora-tb3a was built from this branch's exact tree. Stage 2 was aura b5 + aura#103 with this branch's J616s DTB, booted once through aura-try.
Other Macs: the driver changes only add T6040 match data (the v1 router and PCIe paths are unchanged), and only |
This was referenced Nov 8, 2026
…y helper apple_cio_pcie_tunnel_is_preinitialized() now calls apple_cio_pciec_eligible(), which also admits apple,t6040-pciec. Pull the helper into the test build and take a const node in the fixture's of_device_is_compatible(), as the kernel's does. Assisted-by: LLM Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com>
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USB4/Thunderbolt on the J616s (M4 Pro, 16-inch) left back port, ACIO0. Integration already carries the T6040 router, DART and NHI description, disabled and with the NHI ring interrupts fixed (#1212). This PR adds what is still missing and enables port 0 on the J616s only.
thunderbolt: apple/PCI: apple: the driver half of PCI: apple: draft T6040 USB4 tunnel resources #1052 (T6040 v2 router, Type 7 NHI, T6040 PCIe-C data). The diff is byte-identical to the code that ran in TB2's trial 5b.phy: apple: t6040: CIO mode. This is AxxzyWasTaken's commit from phy: apple: t6040: CIO mode, and the T6041 USB4 resources #1126, cherry-picked with his authorship and Signed-off-by.apple,t6041-cio-reset, plus LSTX forapple,t6040-usb4-acio.t6040-usb4.dtsiand the J614s/J616s boards (from arm64: dts: apple: j614s/j616s: wire the USB4 routers (disabled) #1165): each router gets its CIO reconfig reset and LSTX pin, and each Type-C connector is linked to its router in the graph. The CIO reconfig block now uses the T8132 PMGR compatibles. The aliases are renamedusb4-N-acio, which is the name aura looks up for the router tuning. Nothing is enabled in this commit.t6040-j616s.dts: enables ACIO0, its DART (ADT vm-base window), NHI, mailbox, CIO reconfig and power domains. There is no PCIe tunnel yet, so this covers host-to-host (XDomain, thunderbolt-net) and USB4 links.Not included: #946's
b9fcf33(T8110 DART set up from scratch) and the router-DARTapple,bypass-sids/full-error-reporting/ctc-flushprops. The proof boot below runs without them (this was the trial 5c ablation).J616s board DTB vs production Stage 2 DTB (b975817a), semantic diff: only the USB4 nodes above and the #1212 IRQ fix changed. Everything else is phandle renumbering.
Hardware proof (J616s <-> M2, TB5 cable): results are posted as comments below.
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