[RyanTheTide]

Ryan wants USB4/Thunderbolt on every J616s USB-C port. #1220 enabled only the left back port (ACIO0). This PR enables ACIO1 (typec1, left front) and ACIO2 (typec2, right) the same way: router, its DART with the ACIO0 DVA window, NHI, mailbox and power domains, PCIe tunnel off. The resets, LSTX pins, ring interrupts (#1212) and Type-C graph links are already in place, and aura already hands every router its tuning and DROM.

The semantic DTB diff against the J616s production Stage 2 DTB (fe33cf4f, fleet42) shows only these nodes.

Proof per port (J616s fleet42 with an aura-try trial of this DTB, M2 on fleet42; each port is ticked when its run passes):

• left front (ACIO1) <-> M2 rear port: link at boot, 2 x 20 Gb/s, thunderbolt-net ping 0.23 ms, iperf3 J616s->M2 18.9 / M2->J616s 19.5 Gbit/s, 5/5 rtcwake s2idle with networking back, err 0, AVC 0. The dock on the left back port (non-USB4) keeps working with ACIO0 enabled.
• left front, both orientations (Ryan replugged and flipped the cable, 11-09 ~14:45): reverse (PHY lane 1) iperf3 19.0 / 19.6 Gbit/s, normal (lane 0) 18.5 / 19.6 Gbit/s
• right (ACIO2): link at boot, iperf3 18.0 / 19.1 Gbit/s, physical unplug/replug, link back about 6 s after plug-in. The PHY logs show normal orientation each time.
• left back (ACIO0) on this DTB: iperf3 18.5 / 19.4 Gbit/s, physical replug, link back about 17 s after plug-in. Flipped to reverse: 18.1 / 19.5 Gbit/s.
• M2 partner, rear and front ports, in both orientations each: 17.3-20.5 Gbit/s
• Every step: dmesg 0 errors on both Macs, 0 AVC. Trial Stage 2 195b4260 = production 478e08a9 with this DTB, on fleet44.

🤖 Generated with Claude Code