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J616s: USB4/Thunderbolt on the left front and right ports (ACIO1, ACIO2) #1263

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Merged
RyanTheTide merged 1 commit into from
Nov 9, 2026
Merged

J616s: USB4/Thunderbolt on the left front and right ports (ACIO1, ACIO2) #1263

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77 changes: 74 additions & 3 deletions arch/arm64/boot/dts/apple/t6040-j616s.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -167,9 +167,10 @@
};

/*
* USB4/Thunderbolt on the left back port (typec0, ACIO0). The loader hands
* the router, adapter and NHI tuning and the DROM over. No PCIe tunnel yet:
* host-to-host (XDomain, thunderbolt-net) and USB4 links only.
* USB4/Thunderbolt on all three Type-C ports: typec0 (left back, ACIO0),
* typec1 (left front, ACIO1) and typec2 (right, ACIO2). The loader hands
* each router its router, adapter and NHI tuning and its DROM over. No PCIe
* tunnels yet: host-to-host (XDomain, thunderbolt-net) and USB4 links only.
*/
&pmgr_cio {
status = "okay";
Expand Down Expand Up @@ -209,3 +210,73 @@
&usb4_0_nhi {
status = "okay";
};

&ps_atc1_cio {
status = "okay";
};

&ps_atc1_pcie {
status = "okay";
};

&ps_atc1_cio_pcie {
status = "okay";
};

&ps_atc1_cio_usb {
status = "okay";
};

&usb4_1_mbox {
status = "okay";
};

&usb4_1_acio {
/delete-property/ apple,pcie-tunnel;
status = "okay";
};

&usb4_1_dart {
/* The same DVA window as the ACIO0 router DART. */
apple,dma-range = <0x100 0x4000 0x0 0xffff0000>;
status = "okay";
};

&usb4_1_nhi {
status = "okay";
};

&ps_atc2_cio {
status = "okay";
};

&ps_atc2_pcie {
status = "okay";
};

&ps_atc2_cio_pcie {
status = "okay";
};

&ps_atc2_cio_usb {
status = "okay";
};

&usb4_2_mbox {
status = "okay";
};

&usb4_2_acio {
/delete-property/ apple,pcie-tunnel;
status = "okay";
};

&usb4_2_dart {
/* The same DVA window as the ACIO0 router DART. */
apple,dma-range = <0x100 0x4000 0x0 0xffff0000>;
status = "okay";
};

&usb4_2_nhi {
status = "okay";
};
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