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PCI: apple: draft T6040 USB4 tunnel resources - #1052
RyanTheTide wants to merge 6 commits into
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Describe the disabled T6040 ACIO v2, Type 7 NHI and PCIe-C topology, and add the verified register and shared-MSI generation data. Assisted-by: LLM Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com>
Use the captured 16 KiB wrapper window instead of extending the older ACIO SRAM span, and allow the six documented PCIe-C interrupts in the common schema limit. Assisted-by: LLM Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com>
Picks up the tools/aurora-sep source-check fix (c60537c) and the current release branch, so CI runs against today's base. Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com> Assisted-by: LLM
…ader The boot loader copies each router's PCIe adapter tuning to the node behind the usb4-N-pcie-adapter alias. T6040 had no such alias, so the adapter stayed untuned even with the router enabled. Point it at the router node, whose "pcie-adapter" register range the driver applies it to. The hyphenated spelling adds no dtc alias warnings. Checked: t6040-j616s.dts preprocesses and compiles, with the same 11 dtc warnings as before (all pre-existing underscore alias names). Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com> Assisted-by: LLM
…gment The "sram" window of each T6040 USB4 router was the 16 KiB at cpu+0x8000. That is the router's ASC mailbox, which the mailbox node already claims, so the router could not map it, and it is not where the firmware keeps its shared buffers. The ADT names the real region. The router's RTKit nub (acio-cpuN / iop-acioN-nub) lists its preloaded segments, and __DATA sits at cio+0x1080000, 0x26000 bytes, at IOVA 0x10000000. That IOVA is the driver's APPLE_CIO_SRAM_IOVA_BASE, and the shape matches T8103/T8132 (0x...1080000, 0x20000) and T6050 (0x26000). Use that window on all three routers. Checked: the J614s and J616s DTBs build with the same dtc warnings, and nothing else in them uses this range. Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com> Assisted-by: LLM
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Two fixes pushed here (TB lane, 2026-11-08):
Also: the boot loader disabled these nodes because of an aura bug, not because of anything in this PR. For 🤖 Generated with Claude Code |
…ound The ADT lists each router's NHI interrupts as twelve higher numbers, twelve lower ones and the SRAM parity line (acio0: 1774-1785, 1762-1773, 1791). The lower twelve are the TX rings and the higher twelve the RX rings, as the T6050 router description that works on the J716c maps them. The T6040 nodes had the two halves the other way round, so the TX-done interrupt reached the RX handler, which acknowledged the wrong status bit; the level interrupt never dropped. Swap the halves for all three routers. Not yet run on hardware: the J616s link trial that should confirm it is pending. Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com> Assisted-by: LLM
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J616s to M2 USB4 link works with this branch and one fix. I pushed 89a4f34 to this branch (fast-forward). It swaps the NHI TX/RX ring interrupt halves, which were the wrong way round for all three routers. With the old mapping, the TX-done interrupt reached the RX handler, which acked the wrong status bit. The level interrupt never dropped, and the J616s hung at Trial on the J616s (fleet31 base plus this driver, #1126 PHY CIO mode and a trial DTB with ACIO0 on), cable to an M2 on fleet31:
The trial DTB also set 🤖 Generated with Claude Code |
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Superseded by #1220. Integration already has its own copy of t6040-usb4.dtsi, so merging this branch conflicted. #1220 rebuilds the change on integration: the driver half (byte-identical to the code that ran in trial 5b), the #1165 resets/LSTX/Type-C graph, and the J616s ACIO0 enable. The J616s proof boot (link at boot, 2 x 20 Gb/s, 18.5 Gbit/s thunderbolt-net) is posted on #1220. I'll close this once #1220 merges. |
Take aurora-silicon#1052's fixes, which t6041.dtsi inherits through t6040-usb4.dtsi: the ACIO sram window is now the router's __DATA segment (e0dac7b), the NHI ring interrupts are in the right order, and the PCIe adapters are named for the boot loader. The J616C ADT gives the same __DATA segment on all three ports (acio-cpuN iop-acioN-nub segment-ranges: cio+0x1080000, 0x26000). Signed-off-by: AxxzyWasTaken <axxzytte@gmail.com>
Summary
Safety boundary
All new ACIO, NHI, DART and PCIe-C nodes remain disabled. This draft does not opt into kernel cold initialization, add the missing T6040 PHY transition, or claim a cold ACIO firmware reset path.
Validation
Hardware qualification is deliberately deferred until the PHY/PD and retained-firmware handoffs are implemented and reviewed.