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Add the T6050 DisplayPort/USB combo PHY and four-clock display crossbar profile. Carry the current Type-C, USB2, USB3 PIPE sequencing, and teardown behavior from the published T6050 source. Source snapshot: t6050-gpu ee68abb105200e99636a5edfc647a5cfc1d89954 Integration base: 9cbdd07 Signed-off-by: Dj <hey@djdev.me> Signed-off-by: Erik Bourget <erik@ebourget.net>
The combo PHY's USB2 PHY and digital banks are in the USB controller's power domain. Let a combo PHY name it fourth, as "usb", so the PHY can hold it on a port with no USB controller bound. The fixed DisplayPort PHY keeps exactly three domains. Signed-off-by: Jeff Queisser <funkzy@users.noreply.github.com> Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Signed-off-by: Erik Bourget <erik@ebourget.net>
The combo PHY's USB2 PHY and digital banks are in the USB controller's power domain. Only a bound USB controller holds that domain, so on a port with no controller (a DisplayPort-only port, as on J775D with Linux on the hardware) the first Type-C mode switch wrote an unclocked bank and took an SError. A combo PHY node may now name that domain as a fourth power domain, "usb". When it does, the PHY holds it from combo start to combo stop, after the common domain on the way up and before it on the way down. Nodes that name three domains probe and run exactly as before, and the fixed DisplayPort PHY still takes exactly three. Testing: on J775D (M5 Ultra), with the fourth domain named on each combo port, Type-C mode switches and DisplayPort on the rear ports ran without an SError on every boot since 2026-10-30. Signed-off-by: Jeff Queisser <funkzy@users.noreply.github.com> Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Signed-off-by: Erik Bourget <erik@ebourget.net>
apple,port-index has an enum but no type, so dtschema cannot decode the cell and every combo PHY node fails with "b'\x00\x00\x00\x02' is not one of [1, 2]" and a core-schema type error, whatever port it names. Give it the uint32 type. Signed-off-by: Jeff Queisser <funkzy@users.noreply.github.com> Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Signed-off-by: Erik Bourget <erik@ebourget.net>
Add apple,t6050-dwc3, the T6050 (J775D) DWC3 on bare metal. It uses the shared tunable table, extended with the tables Diljit Singh's T6050 USB support applies, in the same order: the T6040 tables plus CIO (the Apple region from 0xcd20, after the fixed CIO values), bulk fabric and AUSBC debug (the optional drd-bulk and drd-ausbc regions). It is host-only, like T6040. The USB2 port reset follows the root hub's start (a no-op without a PHY reset op), and a USB3 PHY failure is fatal, as on T8132. Signed-off-by: Jeff Queisser <funkzy@users.noreply.github.com> Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Signed-off-by: Erik Bourget <erik@ebourget.net>
The PIPE lock that starts the USB3 handoff is acknowledged only while the combo PHY's dummy PIPE PHY is enabled (pipehandler NONSELECTED_OVERRIDE bit 15), as on the earlier ATC PHYs (T8122, T8140), and the bit resets to clear with the controller's domain. Without it the lock timed out, the PHY faulted and rear port 2 had no USB at all. Enable it before the controller leaves reset. Each PIPE-switch step returns its own code, and every fault of the PHY is logged with its reason (the pipehandler registers for PIPE faults); dwc3-apple logs a fatal USB3 PHY failure. Signed-off-by: Jeff Queisser <funkzy@users.noreply.github.com> Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Signed-off-by: Erik Bourget <erik@ebourget.net>
A USB3 PIPE switch can fail before the mux moves, with the PIPE still on its dummy producer. The PHY then faulted and lost USB2 with it. Leave the port on USB2 in that case, as four DisplayPort lanes do. Signed-off-by: Jeff Queisser <funkzy@users.noreply.github.com> Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Signed-off-by: Erik Bourget <erik@ebourget.net>
The combo PHY refused any apple,port-index other than 1 or 2, the two ports a guest description produced. Nothing else in the driver reads the index: the firmware buffer, banks and sequences are port-agnostic. Validate it against the board's port set instead: 1 to 5, with 0 (the port that carries the boot loader's debug link) still excluded, here and in the binding. Signed-off-by: Jeff Queisser <funkzy@users.noreply.github.com> Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Signed-off-by: Erik Bourget <erik@ebourget.net>
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DjDeveloperr
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Works on the M5 Pro (MacBook Pro 14", J714sAP, T6050), bare metal.
This head (c24e75c) on PR1012's base, with the other T6050 platform PRs, on three boots:
- Both Type-C combo PHYs register (
phy-2ab000000.phy.0-2,phy-383000000.phy.3-5). Both DWC3s bind (2aa280000.usb, 382280000.usb), and typec port0 and port1 come up with the sn201202x controllers. No PHY or dwc3 errors. - The debug port (ATC0, our KIS link) is left alone and stayed up the whole time.
This was without our local J714s "0x22 dummy PIPE" commit, and there was still no fault: on today's boot chain (Stage 1, then aura Stage 2 from the ESP) the cold park didn't meet 0x22. A kernel with #946's 6f93def on top also binds both ports. That commit is the general fix for a boot without the SPTM, so it would fit here rather than in #946, though J714s doesn't need it today.
Not tested: USB data (nothing is plugged into ATC1/ATC2, and ATC0 is the debug link), DisplayPort.
Merge note: this head conflicts with current integration/aurora in apple,display-crossbar.yaml, apple,dwc3.yaml and apple-display-crossbar.c, where integration has added T6050 compatibles and the T8132 crossbars (e0b7106, f67926c, 95246f2). For the test I resolved them keeping both sides.
RyanTheTide
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RyanTheTide
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This conflicts with current integration/aurora in the apple,display-crossbar and apple,dwc3 bindings and drivers/mux/apple-display-crossbar.c (the T6050 compatibles added in e0b7106 and later). Could you rebase it? No CI has run on this branch yet; the push after the rebase will run dt-checks and the host tests.
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Closing: merged as part of #1323 (f030e40), which carries these eight commits rebased onto integration/aurora with Ryan's conflict resolutions (R1 crossbar, R2 🤖 Generated with Claude Code |
integration/aurorahas no T6050 Type-C PHY, so the USB-C ports have no USB. This adds DJ's DisplayPort/USB combo PHY (his commit from #480, without its APIF test scripts) and the bare-metal DWC3, plus the fixes found bringing them up:apple,port-indexgets its uint32 type in the binding.Commits by Dj and Jeff Queisser. On J716c (MacBook Pro 16-inch, M5 Max) this runs as part of the full T6050 stack (
j716c/t6050-platform): the machine boots to userspace from NVMe with all 18 CPUs, N1 Wi-Fi up and CPU frequency scaling active. On J716c this PHY also carries the Thunderbolt PR's CIO mode.Created with Claude Opus 5.5 in Claude Code.