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arm64: dts: apple: add the J716s (MacBook Pro 16-inch, M5 Pro) - #1167
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RyanTheTide merged 26 commits intoNov 8, 2026
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Add the T6050 SoC in its two-die M5 Ultra form, and the Mac Studio board that uses it: the device tree for Linux running on the hardware, as the boot loader hands it over (the loader fills the tunables and calibration the nodes name). Every T6050 is made of the same die, so the SoC description is split as for the M3 Max and Ultra (t6031-base, -die0, -dieX): - t6050-base.dtsi: the nodes common to every size, die 0's bus and the CPU node template; - t6050-die0.dtsi: the blocks used on die 0 only, among them the interrupt controller that serves both dies; - t6050-dieX.dtsi: the per-die template, included once for each die, with each die's blocks at the die stride and its interrupts on its own die of the AIC; - t6050-ultra.dtsi: the two dies, their CPUs (five cores in each cluster) and the blocks so far described for the two-die part only: the video decoders, the memory cache controllers, the display subsystem, die 1's ATC0 and its DisplayPort PHY; - t6050-j775d.dts: the board, its USB-C ports and their PD controllers, the HDMI port, PCIe, audio, the boot NOR and the fans. Signed-off-by: Jeff Queisser <funkzy@users.noreply.github.com> Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> [erik: dropped references to private files from a comment] Signed-off-by: Erik Bourget <erik@ebourget.net>
Build t6050-j775d.dtb, the Mac Studio with the M5 Ultra (J775D, T6050), with the other Apple device trees. Signed-off-by: Jeff Queisser <funkzy@users.noreply.github.com> Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Signed-off-by: Erik Bourget <erik@ebourget.net>
T6050's coprocessors (ANS among them) use the ASC v4 mailbox. Signed-off-by: Jeff Queisser <funkzy@users.noreply.github.com> Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Signed-off-by: Erik Bourget <erik@ebourget.net>
Add the J775D board and its T6050 (M5 Ultra) SoC. Signed-off-by: Jeff Queisser <funkzy@users.noreply.github.com> Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Signed-off-by: Erik Bourget <erik@ebourget.net>
T6050's AIC3 is the T8122 one with two dies, so it takes the T8122 fallback and, like T6031's, four interrupt cells (the second is the die). Signed-off-by: Jeff Queisser <funkzy@users.noreply.github.com> Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Signed-off-by: Erik Bourget <erik@ebourget.net>
T6050's watchdog is compatible with T8103's. Signed-off-by: Jeff Queisser <funkzy@users.noreply.github.com> Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Signed-off-by: Erik Bourget <erik@ebourget.net>
Add apple,t6050-dart, the DART of the T6050 (M5 Ultra) PCIe ports and display co-processors, with the t8110 fallback like the other recent SoCs. Signed-off-by: Jeff Queisser <funkzy@users.noreply.github.com> Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Signed-off-by: Erik Bourget <erik@ebourget.net>
T6050's boot NOR sits behind a QSPIMC controller with the same P and C apertures (C at P + 0x800) as T8140's. Describe it as "apple,t6050-qspi", "apple,t8140-qspi" so the driver's T8140 policy (data reads anywhere, programs and erases only inside the nvram partition) applies without a driver change. Signed-off-by: Jeff Queisser <funkzy@users.noreply.github.com> Signed-off-by: Erik Bourget <erik@ebourget.net>
The PMU's info-pm_setting byte (0x2001, as on T6030) holds the power-on
policy: bit 0 keeps the machine off when power returns after a loss, bit 5
keeps it off when power is connected. Hand it to the SMC reboot node as the
pm_setting cell so macsmc-reboot's ac_power_mode can read and set it.
Written 0x03 ("always") from Linux on the Studio, a wall-power cycle after
a Linux shutdown powered it on by itself.
Signed-off-by: Jeff Queisser <funkzy@users.noreply.github.com>
Signed-off-by: Erik Bourget <erik@ebourget.net>
Add t6050-max.dtsi, the one-die M5 Max: die 0 of the T6050, with six cores in each cluster, 18 in all, and the MTP, so far described for this part only. Add the J716c board on it. Described so far: the CPUs, AIC, NVMe, the SMC, the boot framebuffer, the DockChannel console and the keyboard and trackpad (MTP). The GPU, video decoder and memory cache controllers are not described for the Max yet; the internal PCIe host, USB-C, I2C, the SMC sensors and pinctrl_ap stay disabled until each is brought up on this board. Developed with Claude Code. Signed-off-by: Erik Bourget <erik@ebourget.net>
On J716c, reading pin 112 of the AP pin controller takes an SError. Use the uncached regmap on T6050, as on T8140 and T8132, so that only the pins a board names are ever read. Developed with Claude Code. Signed-off-by: Erik Bourget <erik@ebourget.net>
The boot loader trains port 0 (the N1 Wi-Fi/Bluetooth); describe it with its PERST# on pinctrl_ap pin 80. Pin 112 of pinctrl_ap takes an SError when read, so pin 80 is the only one exposed. Developed with Claude Code. Signed-off-by: Erik Bourget <erik@ebourget.net>
The 14-inch M5 Max is the same one-die T6050 as the J716c, so the board file reuses t6050-max.dtsi and enables the set the J716c file enables: CPUs, AIC, NVMe, SMC, boot framebuffer, DockChannel console, keyboard and trackpad, and the N1 Wi-Fi/Bluetooth on PCIe port 0. This PR is stacked on the J716c device tree PR (aurora-silicon#945). Three values differ from the J716c file: - the N1 firmware name and platform ID (j714c-ftab.bin, board 0x0a), - the trackpad firmware (tpmtfw-j714c.bin), - the trackpad AFE reset is owned by the MTP firmware (power method 2, apple,firmware-managed-reset), so the board has no smc_pcio reset line. Add the apple,j714c compatible to the binding. Signed-off-by: Joshua Warren <816217+joshuaswarren@users.noreply.github.com>
t6050-max.dtsi lists the sixth core of each cluster (cpu5, cpu11, cpu17) after the other fifteen. m1n1's dt_set_cpus() walks the CPU nodes in order and compares node N with the core the ADT lists as cpu N; it only prunes nodes of cores that are not alive and otherwise refuses to boot on the first mismatch. On the J716s (M5 Pro), whose ADT lists all 18 cores cluster by cluster, the boot stopped with FDT: DT CPU 5 MPIDR mismatch: 0x40100 != 0x40005 List the cores in the ADT's order, which is also the order of the labels (cpu5 is 40005, cpu11 is 40105). A part with a core fused off still lists it in the ADT and m1n1 prunes its node, so the order holds there too. The device tree passed to Linux then numbers the CPUs as the ADT does. t6050-ultra.dtsi (J775D) has the same layout per die and is left alone here: no J775D ADT was available to check its order. The J716c and J714c use the same file; neither was booted with this change. Tested on J716s: all 18 cores come up. Signed-off-by: Rolando Trevino <rolotrealanis@gmail.com> Assisted-by: LLM Claude
The T6050 SMC has a second bank of GPIO keys, the lower-case gp keys, as T6030 and T6031 do; on the J716s macsmc-low-gpio finds gp01 as its first key. gpio-macsmc drives it as "apple,smc-low-gpio", and the MFD core registers the bank only when this child node exists. Describe it next to the other SMC children as "gpio-low", the node name apple,smc.yaml documents and t6041-j616c.dts uses, with the label the T6030 and T6031 files use. The J716s trackpad's AFE reset is on it (gp1c). Tested on J716s. Signed-off-by: Rolando Trevino <rolotrealanis@gmail.com> Assisted-by: LLM Claude
The J716s (Mac17,8 in its ADT) is a MacBook Pro with one T6050 die, the M5 Pro. Add its board compatible. Signed-off-by: Rolando Trevino <rolotrealanis@gmail.com> Assisted-by: LLM Claude
The PWM controller on the Apple T6050 (M5 Pro/Max) is compatible with the t8103 (M1) one: on the J716s it drives the keyboard backlight through the apple,s5l-fpwm driver unchanged. Add "apple,t6050-fpwm" as its per-SoC compatible. Signed-off-by: Rolando Trevino <rolotrealanis@gmail.com> Assisted-by: LLM Claude
The T6050 (M5 Pro/Max) SPMI controllers are the T8142 generation-4 controller: the T6050 device trees describe their nub-spmi buses as "apple,t6050-spmi", "apple,t8142-spmi", and spmi-apple-controller drives them through the T8142 entry (the J716s Type-C controllers sit on one). Allow that pair. Signed-off-by: Rolando Trevino <rolotrealanis@gmail.com> Assisted-by: LLM Claude
The T6050 (M5 Pro/Max) device trees describe the PMGR power state registers as "apple,t6050-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate", and the pmgr-pwrstate driver handles them through the T8103 entry, as for the other SoCs after T6000. Add the per-SoC compatible. Signed-off-by: Rolando Trevino <rolotrealanis@gmail.com> Assisted-by: LLM Claude
The T6050 (M5 Pro/Max) PMGR blocks are described as "apple,t6050-pmgr", "apple,t8103-pmgr", "syscon", "simple-mfd" in the T6050 device trees, like the other SoCs after T6000. Add the per-SoC compatible. Signed-off-by: Rolando Trevino <rolotrealanis@gmail.com> Assisted-by: LLM Claude
The T6050 (M5 Pro/Max) cluster DVFS block has the T8112 register layout: on the J716s the status register at +0x50 carries the current p-state in bits 9:5 and the target in bits 4:0, as on T8112, and apple-soc-cpufreq drives all three clusters through the "apple,t8112-cluster-cpufreq" fallback with max_pstate 31. Allow "apple,t6050-cluster-cpufreq" with that fallback, as for T6020, T6030, T6031, T6041 and T8122. A driver entry for T6050 itself (the t6050/cpufreq branch has one, with transition verification and a firmware thermal requirement) matches the first string and takes precedence without a device tree change. Signed-off-by: Rolando Trevino <rolotrealanis@gmail.com> Assisted-by: LLM Claude
The J716s is the M5 Pro MacBook Pro 16-inch: one T6050 die, as the J716c (M5 Max), on the same SoC description (t6050-max.dtsi). The board file starts from t6050-j716c.dts and adds what the J716s ADT shows to differ and what has been brought up on it: - the N1 on PCIe port 0 with this board's platform ID (board-id 0x0c); - the keyboard backlight (FPWM0) and its power state, which t6050-die0.dtsi does not describe yet; - the left-front Type-C port (ATC1): the SN201202x hpm1 on nub-spmi-a0 and the connector graph into dwc3 and the combo PHY; - the right Type-C port (ATC2): nub-spmi-a1, which t6050-die0.dtsi does not describe yet, the SN201202x hpm2 on it, ATC2's combo PHY, mailbox, power states, dwc3 and DARTs, and the connector graph. Only the USB route; the DisplayPort route through ATC2 stays off; - the SMC sensors: the shared fan, power, voltage and current keys and temperature discovery, with the T6050 fan mode keys F0md/F1md; - the trackpad's AFE reset on SMC GPIO gp1c (active low), the line the J716c drives through the pcIO output; the pcIO node is deleted; - the T8112 DVFS fallback on the three cluster nodes (the blocks have the T8112 status layout); a T6050 driver entry takes over from it; - ATC3's USB chain and nub-spmi-a2 disabled (the ADT has neither). The debug port (ATC0) is not described. Tested on J716s with the same nodes plus a gadget on the debug port: NVMe root, keyboard and trackpad, USB3 on both Type-C ports, network, SMC (battery, AC, fans and temperatures), 18 CPUs scaling through the T8112 fallback. Signed-off-by: Rolando Trevino <rolotrealanis@gmail.com> Assisted-by: LLM Claude
The J716s boots with no modules on its root file system, so every driver on its boot path has to be built in. Add the fragment it is built with on top of defconfig and asahi.config: make ARCH=arm64 LLVM=1 defconfig asahi.config j716s.config Besides the storage, SMC, HID, Type-C, Wi-Fi and Bluetooth drivers it turns Rust off (nothing on this machine's path needs it yet), keeps the MTP haptic driver off so that HID_MAGICMOUSE, which drives the trackpad, can be built in, and enables Landlock (pacman's download sandbox), nftables, zram with zstd and /dev/mem for the userspace it runs. Signed-off-by: Rolando Trevino <rolotrealanis@gmail.com> Assisted-by: LLM Claude
This was referenced Nov 7, 2026
Integration now has the T6050 base, J775D, J716c and J714c from aurora-silicon#935 and aurora-silicon#945 with their review fixups. This branch carries earlier copies of those commits, so the shared files conflicted: - t6050-max.dtsi keeps this branch's CPU order and takes the MTP helper compatible from integration; - t6050-die0.dtsi keeps the SMC's second GPIO bank; - the J775D, J716c and J714c files, the QSPI and SPMI bindings take the reviewed versions from integration; - arm/apple.yaml lists the J716s in its own M5 Pro entry, the Makefile builds it next to the other T6050 boards. Assisted-by: LLM Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com>
The tree builds every Apple Silicon Mac from one configuration, defconfig plus asahi.config, and keeps no per-board fragments. An option the J716s needs belongs in asahi.config, and building the boot path into the image instead of modules is a choice for the distribution's config. Assisted-by: LLM Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com>
The boot loader always passes the command line, so "maxcpus=1" never applies on a normal boot and would only hide cores when it did, as on the other T6050 boards. Assisted-by: LLM Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com>
Contributor
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Thanks for this, and for booting it on a real J716s. Ryan wants the T6050 trees in, so this PR is in scope and I've pushed our fixups on top. Your commits stay as they are. What I checked
What I pushed
On your open questions
Build-tested here, and you've booted it on the J716s, so this goes in once CI is green. |
RyanTheTide
merged commit Nov 8, 2026
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Integration now has the T6050 base and the J775D, J716c, J714c and J716s trees from #935, #945 and #1167. arm/apple.yaml conflicted: the K boards go into the M5 Pro and M5 Max entries next to the J714/J716 boards. The pwm and pmgr-pwrstate bindings already list T6050. Assisted-by: LLM Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com>
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Thanks for the review and the fixups. Dropping |
DjDeveloperr
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arm64: dts: apple: t6050-j716s: let the kernel train the N1 root port (on #1167)
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The M5 Pro MacBook Pro 16-inch: one T6050 die, like the J716c, on t6050-max.dtsi.
The first 13 commits are #945 (with #935) as they stand today, cherry-picked onto integration/aurora (only the qspi binding needed a conflict fix: enum [t6050-qspi, t8152-qspi] + const t8140-qspi); they drop out once #945 lands.
New here:
Tested on J716s: this exact DTB plus a local node for the debug-port gadget (our tether), on integration/aurora 7.3 with the T6050 series: NVMe root, keyboard and trackpad (DockChannel MTP), USB3 on both Type-C ports (SuperSpeed Plus on the right port, hot-plugged), network, SMC battery, fans and temperatures, the N1 adopted with Wi-Fi and Bluetooth, 18 CPUs scaling through the T8112 fallback, s2idle. Not booted on J716c or J714c.
Checks: make dtbs clean, W=1 clean for the four T6050 boards, dt_binding_check clean for the touched bindings. dtbs_check on t6050-j716s.dtb: 53 lines, none from a node this file adds; the rest are the T6050 bindings that live in #936, #938, #939, #941, #946 and #481 (J716c on the same tree: 58).
Dependencies: #945 (contained). Runtime: #936 (NVMe), #939 (combo PHY, dwc3), #941 (SMC), #937/#938 (N1). cpufreq: with #481, its T6050 entry takes over from the fallback; if #481 lands first, the fallback override and its binding line can go instead.
Open questions: whether you prefer this stacked on the j716c/dt branch instead of carrying #945; a
panelnode for the boot framebuffer (the file has none, so the connector reports as Unknown rather than eDP); trackpad AFE reset via gp1c (tested) vs the pcio template route once #941 lands.