[erikwb]

There's no device tree for T6050 (M5 Max and M5 Ultra) when Linux runs directly on the hardware. This adds the T6050 SoC files and the J775D Mac Studio board, as the boot loader hands the machine over, plus the compatible-only binding updates the tree needs.

Every M5 size is the same apple,t6050, so the SoC is described once and sized per part:

• t6050-base.dtsi: what every size shares (the CPU and per-die address macros, clocks, die 0's bus);
• t6050-die0.dtsi: the blocks only die 0 has;
• t6050-dieX.dtsi: the per-die blocks, included once per die;
• t6050-ultra.dtsi: the two-die M5 Ultra, which J775D includes. The J716c PR adds t6050-max.dtsi for the one-die M5 Max; a binned or smaller part can include that the way t6034.dtsi includes t6031.dtsi.

The binding updates:

• apple,t6050-asc-mailbox, AIC3 (apple,t6050-aic3, T8122 fallback, four cells), watchdog, DART (apple,t6050-dart, T8110 fallback) and QSPI (T8140 fallback, so its nvram-only write policy applies);
• the J775D board compatible;
• the PMU's power-on policy cell, which the SMC series' ac_power_mode uses.

The drivers that bind to the new nodes are in separate PRs (NVMe, PCIe, N1, combo PHY, dptx, SMC, cpufreq); this tree compiles without them.

Commits by Jeff Queisser. On J716c (MacBook Pro 16-inch, M5 Max) this runs as part of the full T6050 stack (j716c/t6050-platform): the machine boots to userspace from NVMe with all 18 CPUs, N1 Wi-Fi up and CPU frequency scaling active. The J716c board tree is a separate PR.

Created with Claude Opus 5.5 in Claude Code.

[RyanTheTide]

Review from the Aurora side. Ryan asked for the T6050 device trees in integration, so this PR is in scope now and I've pushed our own fixups on top of the branch. Your commits are untouched, it's all new commits plus one merge.

What I checked

• Every die 0 register window and interrupt in the J775D tree against the J775D ADT and the live J873s ADT. They match, apart from the usual unions (QSPI P+C, the ATC PHY core window, the SMC SRAM from iop-smc-nub). The CPU nodes are in the ADT's order.
• make W=1 on the merged tree: no dtc warnings.
• CHECK_DTBS=y on every Apple DTB against current integration: the branch added 200 schema warnings, all from T6050 compatibles and properties that no binding listed yet. With the fixups it adds none.
• dt_binding_check on every binding the fixups touch.

What I pushed

• A merge of current integration (the Makefile and the QSPI binding conflicted).
• dt-bindings: the T6050 compatibles in the shared Apple bindings, with the fallbacks the tree uses, plus the T6050 properties (firmware-managed thermal on the cluster controllers, the dwc3 CIO tunable, the crossbar's second power domain, the pm_setting cell, the DisplayPort PHY PLL settings, ports the boot loader trained). ANS on T6050 has no power domain or reset in the binding now, as the tree says.
• dt-bindings: new bindings for the combo PHY, the SMC pcIO outputs, the N1 control function and the T8152-generation AOP and its audio service.
• J775D: dropped the default bootargs (the loader always passes one, and maxcpus=1 would only hide cores when it didn't) and the ti,bclk-ratio nothing reads.

Not blocking, for later

• A few literal ADT values sit in the DTS (the dwc3 tunables, the DisplayPort PHY PLL settings). Long term we'd rather have the loader fill those from the ADT at boot like the ATC PHY tunables, so a new board needs no hand copy.
• The AOP comment mentions chosen.aurora,t6050-aop=1. Fine as a loader handoff marker, just flagging it since we're cutting down on chosen flags.

Build-tested, unbooted. We have no T6050 here. @erikwb could you boot the head of this branch on your J716c once #945 is on top, and @funkzy on the J775D? A boot to a shell with the same dmesg as before would be great. I'll merge once CI is green and won't wait on it, and anything a boot turns up goes in a follow-up.

Merge plan: this one first, then #945 and #1167, then our layer that describes the rest of the T6050 boards (all of it disabled).