perf: integer energy bucket, no float or division in the ADC ISR

[FredM67]

Closes #120.

The ADC ISR kept the energy bucket as a float: every positive zero crossing ran bucket += (l_sumP / n) * f_powerCal[phase] - a 32-bit division plus libgcc float calls - and the load decision compared floats. This makes the whole bucket integer and removes the division from the usual path.

Result in __vector_21

	dev	This PR
Library calls, usual path	__divmodsi4, __addsf3, __subsf3, __mulsf3, __floatsisf, 2× __cmpsf2, 5× __gesf2	none
Contribution at a positive crossing	roughly 900-1050 cycles (libgcc estimates)	~125 cycles (counted from the disassembly)
Threshold comparisons	float compare calls	32-bit compares
basic flash / RAM	8666 / 435	8900 / 435

Flash grows by 234 bytes: the cal / n table (55 bytes) and the fallback path; loop() still links the float library for datalogging, so none of it goes away. RAM is unchanged.

How

• Fixed-point bucket (energy_bucket.h, Arduino-free): 1 unit = 1/16 W × mains cycle, int32_t. The bucket, thresholds and limits become l_… (int32_t, per the naming convention).
• Calibration stays float in calibration.h - nothing changes for users. It is converted at compile time, with a shift chosen so that the largest value fills 16 bits: a typical set { 0.042346, 0.043453, 0.042969 } lands within 0.0006%. validation.h rejects a zero, negative or too large (≥ 8) value.
• No division: (sumP / n) × cal == sumP × (cal / n). n (sample sets per cycle) only takes a narrow range, so cal / n comes from a compile-time table in flash, one entry per phase and per n. The range is derived from the ADC timing: 32 ± 4 at 50 Hz, 26 ± 4 at 60 Hz (observed in practice: 31-33). A cycle outside it (start-up, missing phase) rescales its sum to N_MIN samples - the only path that still divides. Bonus: no truncation from the integer division either.
• Multiply: multU24x16_to32_hi8() in mult_asm.h, (a × b) >> 8 with a on 24 bits, six hardware multiplies instead of a 64-bit __muldi3.
• Sign symmetry: rounding is done on the magnitude, half away from zero, so import and export weigh exactly the same.

Tests - written first

test_energy_bucket, 25 native cases (in the CI matrix), each written red against a stub before the implementation:

• calibration shift and rounding; quantisation error < 0.002% from 0.005 to 0.5;
• agreement with the float reference within one unit over the full ±2^18 range, and with the exact energy for every phase and every n of the table;
• no overflow at full scale, exact sign symmetry, no drift over 3000 accumulated cycles, the rescaled fallback.

Mutations that fail it: truncating instead of rounding, a 32-bit product, an off-by-one on n.

test_mult_asm gains the case for the new multiply. It runs on Wokwi in CI only; locally the routine was built for the Uno and its exact instruction sequence emulated against ~1 M exact products, including all byte-boundary edges.

Before merge

• CI green, including test_mult_asm on Wokwi.
• Bench: regulation unchanged (set point, import/export), n_lowestNoOfSampleSetsPerMainsCycle ~32, bucket value in the serial output as before.

Notes

• The CT filter (alpha / lpf_gain) is still float but disabled at compile time; enabling it would bring floats back into the ISR.
• feat: decide the loads just before L1's zero crossing, on a predicted bucket #162 (predictive switching, draft) is based on the float bucket and needs rebasing onto this; its prediction then becomes integer too.

Merge order

Three PRs are open against dev; checked with git merge-tree:

1. feat: support several remote load units #160 (multiple remote units) and perf: integer energy bucket, no float or division in the ADC ISR #163 (integer energy bucket), in either order. The code merges cleanly; the second one only needs a small fix-up in .github/workflows/build.yml (test matrix) and test/README.md (test tables), where both add entries to the same lists.
2. feat: decide the loads just before L1's zero crossing, on a predicted bucket #162 (predictive switching) last, rebased onto dev after perf: integer energy bucket, no float or division in the ADC ISR #163. That is a real rework, not only a text conflict: its prediction uses the float bucket, and must move to Energy::contribution() and the cal / n table - which also removes its extra ISR cost.

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