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feat(sim): count samples filed under the wrong ADC channel - #170

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FredM67 merged 1 commit into
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sim/adc-sequence
Sep 30, 2026
Merged

FredM67 merged 1 commit into
devfrom
sim/adc-sequence

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@FredM67 FredM67 commented Sep 30, 2026

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Summary

The grid simulation now counts ADC samples filed under the wrong channel, and the scenarios expect none.

Why

The firmware files conversions as V1 I1 V2 I2 V3 I3 in turn. It writes ADMUX at the end of its ISR, for the conversion after next. When an ISR runs past the start of that conversion, the conversion runs on the previous channel, and its result is filed under the wrong one. For example, a V2 sample is used as I2.

No sample is lost: the next ISR starts straight away and reads the pending result. So minSampleSets/MC stays at 32, and the datalog cannot show the problem.

How

grid_sim follows the firmware's sequence and flags every conversion whose channel is not the one the firmware files it under. The first two rounds after the ADC starts are ignored while ADMUX's two-conversion pipeline fills up. The three scenarios now include expect misfiled_samples 0.

Measured (surplus-step scenario, 60 s)

Firmware ISR overruns Misfiled samples
dev before #163 10 10, at datalog time (first at 11.001 s)
dev with #163 0 0
#162 (float prediction) 1928 14

This is more precise than the overrun count, which stays in place as an early warning. Most of #162's long ISR calls pass 1664 cycles by only a little, and ADMUX is still written in time.

Testing

🤖 Generated with Claude Code

The firmware files the conversions as V1 I1 V2 I2 V3 I3 in turn and writes
ADMUX at the end of its ISR, for the conversion after next. When the ISR
runs past the start of that conversion, it runs on the previous channel and
its sample is filed under the wrong one.

grid_sim now follows the firmware's sequence and counts those conversions
(ignoring the first two rounds after the ADC starts), and the scenarios
expect none: `expect misfiled_samples 0`.

Measured on the surplus-step scenario: dev before #163 misfiled 10 samples
(one per ISR overrun, at datalog time), dev with #163 none. It is a more
precise check than the overrun count: of #162's 1928 overruns, only 14
misfiled a sample.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
@FredM67
FredM67 merged commit 2f105e5 into dev Sep 30, 2026
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@FredM67
FredM67 deleted the sim/adc-sequence branch September 30, 2026 18:15
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