feat: decide the loads just before L1's zero crossing, on a predicted bucket

[FredM67]

Refs #161. Needs bench validation before merge.

Problem

A zero-crossing triac driver only fires at the next zero crossing of its own phase. The load decision ran ~1.5 ms after L1's positive crossing, so a load on L1 fired at its negative crossing, 10 ms later, halfway through L1's measurement window. Full analysis in #161.

Change

• When: one sample set after the negative crossing of the phase that crosses last before L1's positive one. That is L2, or L3 with reversed rotation: whichever is negative at L1's positive crossing. The pins are written ~1.6 ms before L1's crossing, clear of the drivers' ±0.2 ms firing windows. L1 and L2 then switch at the start of their measurement windows, and L3 at its negative crossing, before its window starts. No load switches in the middle of its window any more. (No single decision instant can put all three phases on a rising crossing.)
• On what: a predicted bucket level, as in Robin Emley's Mk2_fasterControl sketches: the bucket, plus L1's average power so far this cycle, minus the export / start-threshold adjustment. L2's and L3's latest contributions are already in the bucket at that point.
• Integer arithmetic (rebased on perf: integer energy bucket, no float or division in the ADC ISR #163): the prediction is Energy::contribution(L1's partial sumP, cal / n). cal / n for L1's partial sample count comes from a second flash table, for L1 only (23-31 sample sets at 50 Hz, 18-26 at 60 Hz, 18 bytes). There is no float and no division in the ISR.
• Fallback: if no predictive decision was taken during an L1 cycle (start-up, a missing phase, a sample count outside the table), the old decision point is used on the measured bucket.
• A/B switch: PREDICTIVE_LOAD_SWITCHING{ false } in processing.cpp restores the old behaviour.

Thresholds, b_recentTransition, the priority rotation, relays and datalogging are unchanged. processStartNewCycle(), proceedHighEnergyLevel() and proceedLowEnergyLevel() take the decision's energy value as a parameter.

processStartNewCycle() now has two call sites (predictive and fallback) and is noinline. With a single inlined call site at the end of processRawSamples(), the ISR needed a 4-byte stack frame on every call, even with the switch off. The ISR already calls updatePortsStates(), so it saves every register anyway: the extra call costs ~8 cycles, once per mains cycle.

Simulation (grid_sim)

Switching latency (pin write to the zero crossing where the triac switches), clouds scenario:

Load on	dev	This PR
L1	7.70 ms, 0 of 316 at a rising crossing	1.63 ms, 382 of 382 at a rising crossing
L2	4.35 ms, all at a rising crossing	8.29 ms, all at a rising crossing
L3	1.03 ms, at its falling crossing	4.96 ms, at its falling crossing

• Every scenario passes: make check (3 scenarios, 30 expectations) and make check-rf (4 scenarios, 36 expectations, two remote units running the receiver firmware). After start-up, every decision was predictive.
• ADC ISR: average 350.5 → 328.8 cycles, worst case 1389 → 1526 cycles (of 1664), 0 overruns. The worst case is a single event at start-up in both builds. Compared with dev, the ISR pushes one more register (~4 cycles per call) and has no stack frame.
• Control: imported and exported energy and on-times are the same. Where the first load modulates a partial surplus (clouds, sunset), it switches 10-30 % more often, in shorter bursts: less delay in the loop means less overshoot. The grid power per cycle is the same within a few watts.
• Remote loads on L1 don't benefit: their RF frame is sent from loop() after the decision and takes ~1.7 ms on air, so it arrives after L1's positive crossing. They still switch at L1's negative crossing, as on dev.

Cost

	Flash	RAM
basic, emonesp, rf	+308 bytes	+4 bytes
basic_debug	+428 bytes	+4 bytes
basic, switch off	−42 bytes	+2 bytes

Bench checklist

• Scope the triac gate of a load on each phase against its mains voltage, switching on and off: L1's loads switch at its positive crossing, L2's at its positive crossing, L3's at its negative crossing.
• n_lowestNoOfSampleSetsPerMainsCycle stays ~32 (no missed samples).
• Control quality with the switch on vs off: import/export around the set point, number of switching events.
• Reversed phase rotation still triggers on the right phase.

Notes

• Assumes zero-crossing triac drivers / SSRs; with random-phase drivers the original problem does not exist.
• Based on dev after feat: support several remote load units #160 (multiple remote units), perf: integer energy bucket, no float or division in the ADC ISR #163 (integer energy bucket) and ci(sim): run the grid scenarios in parallel #174.

🤖 Generated with Claude Code