PCB design, analysis and project review in KiCad. Choose from 19 independently installable plugins. Processing runs locally after setup. KiCad 10 is the validated target.
| What you need | Where to go |
|---|---|
| Install the tools | Quick steps · Installation guide |
| Run your first analysis | Getting started |
| Download or update | Release 3.6.16 · Release notes |
| Choose a tool | All 19 plugins |
| See the interfaces | Screenshots |
| Find detailed instructions | Full user guide |
| Resolve a problem | Help and upgrades |
| Automate or contribute | Development |
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Open Plugin and Content Manager in KiCad Manager. Add this repository:
https://raw.githubusercontent.com/wayri/WayriCAD/develop/pcm/repo.json -
Select WayriCAD Plugin Repository and install the tools you want. You can also download a PCM ZIP from Releases and use Install from File, without unpacking it.
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For IPC tools, enable the API and configure Python in Preferences → Plugins. Allow the first dependency setup to finish, then restart PCB Editor.
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Open and save your project. Launch a tool from Tools → External Plugins or the toolbar. WayriCAD — All tools… searches the installed tools if the menu is crowded.
Fusion uses the native plugin loader and does not need the IPC API enabled. First-time setup may need internet access. For setup problems or offline use, use the help table below.
| Your first task | Quick start | Detailed guide |
|---|---|---|
| Check voltage drop and copper losses | Quick PI | PI guide |
| Check board and component temperatures | QuickTherm | Thermal guide |
| Screen signal delay and reflections | Quick SI | SI guide |
| Measure route R, L, C and impedance | Trace RLC | RLC guide |
| Edit and export a BOM | BOM workflow | BOM guide |
| Inspect copper and component analytics | Analytics workflow | Analytics guide |
Save the PCB, refill its zones, and save Board Setup before analysis. Start with one net or a small component group, then expand the study. Unknown results mean an input or model is missing; they are not a pass.
- Open WayriCAD Quick PI. In Setup, choose the power net, source pad and sink pad.
- Enter Source · V and Load · A. Add sink voltage limits or Additional sinks if needed.
- Click Preview to inspect the extracted copper, then Run.
- Inspect Results for voltage drop, current density and losses. Choose a layer, hover for values, and click to pin probes. Use Export for HTML and JSON.
For your first run, use the default layered DC model. Review copper thickness, via plating and mesh refinement before relying on local peaks.
- Open WayriCAD QuickTherm. In Component inputs, select the parts to include and enter their actual operating power, not their maximum power rating.
- Use Field mapping… for your property names. Add the thermal resistances and temperature limits needed by the selected model; missing junction paths stay unknown.
- In Board + results, review the board heat model, materials, ambient temperature and environment. Start with a steady-state study and click Run thermal.
- Use Top, Bottom or 3D, probe the board and select parts in the temperature table. Export the report. Add transient power steps after reviewing the steady result.
QuickTherm installs separately from Quick PI. Air, vacuum and other environments need explicit heat-rejection paths; airflow fields are not solved.
- Open WayriCAD Quick SI. Search for a net or use Select net on board.
- Choose source and receiver pads. Review the saved physical stackup and the driver/load assumptions, including rise time and resistance.
- Click Screen selected path. Inspect delay, routed sections, impedance coverage and reflection estimates; unresolved sections remain visible.
- Inspect the route and waveform plots, then export HTML/JSON for review.
Automatic timing assumes ideal continuous references where indicated. A mixed route may have usable section results without a single overall impedance.
- Open Trace RLC / Impedance, choose the net and two different pads.
- Select Path for connected traces/vias/zones, or Zone/plane for a filled island with a declared current-corridor width. Use Auto reference or select a layer.
- Run Analyze, then inspect the copper preview and per-section R, L, C and impedance.
- Export the results. Use Line cross section for manually entered supported CPW, grounded CPW or coupled-stripline geometries.
Automatic board impedance covers supported single-ended microstrip/stripline sections. Differential-pair mode measures paths/skew; it does not automatically extract coupled differential impedance.
- Open WayriCAD Analytics Studio from your saved project.
- In BOM settings, choose fields, grouping, sorting and DNP filters.
- Edit fields in BOM workspace, then save the workspace sidecar.
- Use Exports & templates to preview and export a BOM. Use Review & native sync only when you want reviewed edits written back to the saved KiCad project.
BOM Studio was renamed Analytics Studio; they are one plugin. Existing package IDs and workspace files are retained. Native KiCad exports read saved source; workspace exports can include staged edits.
- Open Board, copper & components in Analytics Studio.
- Review mapped cost, mass and power fields for component analytics.
- Open Board & copper for board area, layer coverage, net/zone copper areas, track lengths, via counts and per-component pad-contact areas.
- Search by net or part, inspect unknowns, and export the tables as CSV, XLSX, JSON or HTML.
Board analytics uses saved geometry and saved zone fills. Pad-contact area means nominal copper land area, not thermal conductance. Missing values and mixed currencies stay explicit.
The IPC packages are 3.6.16; Fusion is 0.9.8, and Variant Manager is 0.6.1. Select a plugin for its full guide and supported models.
| Plugin | Use it for |
|---|---|
| Voltage drop, current flow and copper losses. | |
| Board and component temperatures, heating playback and thermal reports. | |
| Signal delay, reflections, termination and return-path screening. | |
| Route resistance, inductance, capacitance and supported impedance estimates. | |
| BOM editing, purchasing tables and board/copper analytics. | |
| Design rules, netclasses and per-layer routing profiles. | |
| Combine projects or circuit blocks and review linked updates. | |
| Compare, edit, merge and recover assembly variants. | |
| Collect libraries and 3D models for portable projects. | |
| Preview and place escape tracks and vias. | |
| Add reviewed, net-connected stitching vias. | |
| Rename references, fields and PCB text in bulk. | |
| Export pin tables, connector diagrams and signal maps. | |
| Map connectors, cables, bundles and wire requirements. | |
| Add isolated copper patterns for more even copper density. | |
| Inspect 3D collisions, clearances and board assemblies. | |
| Design and preview PCB or foil heating patterns. | |
| Design PCB coils and screen magnetic/actuator behavior. | |
| Check fabrication constraints and prepare manufacturing outputs. |
Current and earlier screenshots are grouped by tool. Click an image for its original resolution. Demonstration inputs are not predictions for your board; older captures retain generic-path redactions. Capture provenance.
Board and results workspace
The displayed field solves a uniform copper plate; the routed PCB provides visual context. Capture and reference.
Package contacts and copper losses · 3.6.14
Generated demonstration board with illustrative lead/solder properties. Capture inputs · Contact model.
Research and model references
| Reference | Role |
|---|---|
| MIT conduction chapter | Analytical resistance checks. |
| Elmer beam fixture | Published numerical benchmark inputs. |
| Full references | Meshing paper, verification guidance and model limits. |
STEP models and transient heating
Calculated board and declared component RC temperatures; each modeled part has one temperature, and grey parts remain unknown. Inputs and validation.
Component inputs
Review power, thermal resistances, limits and analysis scope. Capture notes.
Imported copper/contact heat and fitted controls · 3.6.14
The illustrative 1 s frame includes imported copper and contact losses. Capture inputs · Validation.
Research and model references
| Reference | Role |
|---|---|
| Gmsh research paper (2009) | Optional 3D mesher provenance. |
| CalculiX manual | Thermal backend input format. |
| Full references | Package-model context, bridge and limitations. |
Routed signal analysis
Inspect the selected signal path and its available results.
Protocol screening
Missing models and reference coverage remain visible.
Research and model references
| Reference | Role |
|---|---|
| TI high-speed layout guidance | Protocol/routing context. |
| Nubis SignalIntegrity | Optional network interoperability. |
| Full references | I2C/CAN/DDR sources and shared impedance model. |
Saved-board route analysis
Inspect connected copper and per-section electrical coverage.
AC and geometry analysis
Review the route geometry and conductor-loss estimates.
Research and model references
| Reference | Role |
|---|---|
| Pinned EMerge equations | Scalar cross-section source. |
| Qucs CPW theory | Conformal-mapping equation reference. |
| Full references | Microstrip paper, via/plane sources and validation fixtures. |
Board and copper analytics
Inspect layer/net areas, zones, vias and component pad-contact tables.
Component cost, mass and power · earlier BOM Studio interface
The earlier BOM Studio view is retained here under its current name, Analytics Studio. Missing component data stays explicit.
Rule worksheet
Shipped UI rendered from a demonstration snapshot. Supporting panels open on demand; scope colours are condition matches, not native DRC results.
3D measurements and height checks
The fixture deliberately includes height violations and incomplete coverage. Capture and validation.
Adaptive fanout
Review pads, existing copper and proposed tracks/vias before applying.
Motor EMF and winding analysis
Review winding layouts, motor EMF/force and supported simulation models in the guide.
Research and model references
| Reference | Role |
|---|---|
| Reviewed motor research | Published work and implemented/future model distinctions. |
| Magnetics equation references | Filament and capacitance-matrix checks. |
Assembly comparison
Compare saved and staged assembly states, with bulk operations and reviewed recovery.
| Topic | Guide |
|---|---|
| Missing actions, runtimes or installation paths | Troubleshooting |
| Dependencies and offline use | Runtime setup |
| Tested hosts and known limits | Compatibility |
| What plots, probes and analysis models represent | Analysis interactions |
| Command-line use | CLI guide |
| Repeatable reports and KiCad jobsets | Jobsets |
Refresh PCM, install updates and restart PCB Editor. Keep project backups and BOM workspace files. Remove retired standalone tools to avoid duplicate actions: PDN Decoupling is in Quick PI; Return-Path Auditor and Test Point Descriptor are in Quick SI; Embed3D combines Localizer and Portable Assets.
Hardware planning details are in System requirements.
Use wayricad jobs for repeatable analysis/report sequences and KiCad jobsets.
| Developer topic | Reference |
|---|---|
| Contribution and validation requirements | CONTRIBUTING.md |
| Repository structure and working conventions | AGENTS.md |
| GUI dependencies and offline runtime setup | Runtime setup |
python -m pip install -e ".[test]"
python -m pytest tests -q
python build_pcm.py --output-dir .validation/candidate-pcm
python tools/validate_packages.py --archive-dir .validation/candidate-pcm
Each plugin also has its own tests. Skipped checks do not establish native GUI compatibility. Validation records are in the release audit.
WayriCAD uses AI assistance for development, research and documentation; maintainers remain responsible for validation and releases.
| Project information | Reference |
|---|---|
| Maintainer | Wayri (Yawar) |
| WayriCAD license | GPL-3.0 |
| Fusion and Variant Manager | MIT licensed; see each package's license |
| Credits and AI assistance | Acknowledgements |















