Install · Choose a tool · Routing · Electrical analysis · BOM and libraries · Troubleshooting · CLI
This guide covers the current 24-plugin source catalogue. Released packages and new candidate installers are identified in their individual guides. Screenshots are captures of the applications using example or Marble projects; their values are examples, not predictions for your board. Individual tool guides explain additional controls.
Step-by-step installation guide · Visual installation map
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Open KiCad Manager → Plugin and Content Manager and add:
https://raw.githubusercontent.com/wayri/WayriCAD/develop/pcm/repo.json -
Select WayriCAD Plugin Repository and install your chosen tools. For an offline package file, download a PCM ZIP from Releases and choose Install from File. A ZIP contains one independent plugin.
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Enable the API in Preferences → Plugins and configure the Python interpreter. Allow dependency preparation to finish. Installing a ZIP does not eliminate the first-run dependency requirement.
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Restart the PCB Editor, open and save the project, and launch a WayriCAD action. The action passes the originating editor's project context. File-based processing reads saved files; save recent edits first. Standalone CLI/desktop launches need an explicit project when no editor context exists.
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Start with Preview, Inspect, or the tool's read-only analysis. Review diagnostics before using a write/apply operation.
Help is also shipped inside each package as help.html, with local images. Use the tool's Help action where available, or open that file from the installed package folder. These pages do not need a documentation website or CDN. CLI help is available through each command's --help.
HTML and PDF reports explains browser print, direct PDF export, and common HTML/PDF reports from any tool's saved JSON results.
Runtime boundary: KiCad 10 is the primary target. Some geometry and saved-file engines need KiCad 10 native Python even though the toolbar action uses IPC. KiCad 11-only operation remains unsupported. Exact mechanical solids additionally need FreeCAD. Read runtime setup and compatibility before deploying to another workstation.
The current source UI uses action icons alongside text labels, numbered workflow stages and a visible activity indicator. Icons supplement the labels and tooltips; they do not replace them. These shared controls are used by the quick tools and other native forms that use the common accessibility/workflow helpers.
WayriCAD Assistant is a testing package for local command planning and execution. Select the saved board, describe the task, review the interpreted action and supply requested engineering inputs before running. Results include text, generated artifacts and visual board context. Ambiguous requests need clarification; unsupported commands are reported rather than invented.
In the Assistant board view, selected nets have bright copper highlights while other copper is muted. Focus selected frames that selection; Fit board restores the complete board view. Pad shapes and via holes are retained. Zone borders and conservative arc envelopes remain outlines, not simulated filled copper. Show in PCB Editor explicitly selects the matching net items in the originating editor and requests a zoom. It rejects a changed saved board or a different editor project, and reports when focusing is unavailable. This is selection/navigation, not a geometry edit or validation of unsaved changes. The existing tool CLI remains available for precise scripts. Assistant is included in release 3.6.28 as a testing package.
Select the linked name for detailed instructions. “Review” below means that the output still needs engineering assessment; it is not a manufacturing or electrical sign-off.
| Icon | Tool and detailed guide | Start with | Result and write boundary |
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WayriCAD Assistant | Saved board and a task in plain English | Review a fixed-tool plan, clarify missing inputs, execute supported analyses and inspect reports (testing) |
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Trace Refiner | Selected tracks/nets, net classes or layers | Preview minor jog cleanup, validate native connectivity/DRC, then apply with in-window undo |
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Component Arranger | Selected parts, sheets or confirmed schematic clusters | Preview anchored courtyard-aware group placement and measured crossings; native validation, backed-up Apply and in-window Undo |
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Layer Counter | Enabled copper layers and explicit core pairs | Preview and add grouped physical layer markers plus a zone-only keepout |
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Silkscreen Label Placer | Selected parts or whole board | Preview safe silk labels and guide lines, then apply with undo/redo |
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Project Fusion | Saved projects or selected subsheets | Guided source/variant destination, visual merge, CLI workflows and backed-up offline apply |
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Variant Manager | Native KiCad 10 variant definitions | Assembly comparison, bulk operations, conflict-aware merge/swap, Default promotion and verified recovery |
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Analytics Studio | Saved schematic/project and desired fields | Review staged component data, export purchasing/assembly BOMs; native writes require a reviewed operation |
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Embed3D | Project plus library/model search paths | Preview then copy/relink symbols, footprints and models with backups |
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Quick PI | Net, source/sink pads, voltage/current | Read-only layered DC mesh, fields, losses and risk screening; integrated decoupling placement review; export reports |
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QuickTherm | Saved board, mapped loss fields and thermal resistances | Independent thermal screening with board views, component temperatures and explicit model coverage |
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Trace RLC / Impedance | Connected path or zone terminals and stackup | Read-only trace/via/zone/plane estimates; unknown assumptions stay explicit |
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Quick SI | Signal path, stackup and driver/load assumptions | Delay/reflection/eye screening, return-path review and test-point lists; explicit reviewed test-point silkscreen writes; not a full channel solver |
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Fanout Generator | Footprints/pads, netclass, pattern and layer | Preview candidate escapes/vias, then explicitly apply copper |
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Via Stitching | Net, layer span, region and spacing | Preview accepted/rejected vias, then explicitly apply |
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Bulk Label Editor | PCB text, references, fields and a searchable net inventory | Review/apply text edits; cross-select nets; export tables |
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Pin Extractor | Board/connector scope and fields | Extract pin tables, connectivity diagrams and document exports |
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Harness Workbench | Connector maps and explicit external wire links | Validate and export harness documentation; board connectivity alone cannot infer external wiring |
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Copper Balancer | Saved board, region and density settings | Preview copper thieving, density deficits and rejection counts; save an explicit board copy |
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Mechanical Check | Saved board, component models and enclosure | Quick 2D footprint-envelope screen without FreeCAD; exact-solid checks use FreeCAD; unknown 3D coverage never passes |
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Heater Designer | Region, geometry, material and thermal assumptions | Heater geometry and estimates; review before placement/application |
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Planar Magnetics | Coils, magnetic equivalents, motor windings and declared material/drive inputs | Magnetic fields, capacitance, motor EMF/force and SPICE review; generated copper needs review |
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Manufacturing Readiness | Board, fabricator profile and release inputs | Check reports and explicit DRC/jobset/release operations |
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Constraint Studio | Saved board, protocol assignments and net scope | Inspect rules read-only; stage protocol/matrix/profile changes, review diffs and export a separate bundle. Ordinary rule and netclass editing stays in KiCad. Offline apply requires closed editors and source-hash checks. |
Choose a small component scope first. Set the output mode (escape traces or via-in-pad), layer and geometry. Preview displays pads, existing copper and proposed copper together. Inspect rejected candidates before Apply to board. Changing geometry invalidates the previous review.
Routing → Adaptive preserves existing routes, continues unambiguous open stubs and searches nearby simple escapes using the selected radius and step. It refuses ambiguous topology rather than modifying existing copper. Fixed routing remains available.
Per-pin/net groups let one footprint use different styles, widths, angles, layers or via-in-pad settings. Rules are ordered: the first match wins inside the global scope. Review unmatched/skipped counts rather than assuming every pad was processed.
Via Stitching follows the same preview-first flow with grid pattern, net, layer span, spacing, outline and exclusions. Conservative checks may reject usable locations. Run native KiCad DRC after applying; a clear preview is not a substitute for DRC. The routing CLI provides JSON/SVG plans, writes a new board on apply, and can compare native DRC reports before and after.
For a via fence, choose Guard selected routes, then select exact signal nets or capture selected PCB tracks. Choose a distinct guard net, pitch and centre-to-centre offset. Check Before/After, accepted counts and rejection reasons before Apply. Planning is cancellable and uses a private snapshot; save changes before fast preview. See guard workflow and limits.
| Detailed walkthrough | Coverage |
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| Quick PI user guide | DC and return paths, AC losses, PDN and transient studies, inspection and reports |
| Quick SI user guide | Route screening, return review, neighbour coupling, differential timing and IBIS circuit export |
| QuickTherm user guide | Component inputs, environments, thermal backends, transient playback and reports |
In Quick PI, select the actual power net and source/sink pads. Set source voltage and sink current. Preview extracted copper, inspect layer coverage, then run the mesh solve. Check the Net, Mesh and Results views before interpreting voltage drop, current density or loss.
These captures use a selected Marble path; they are not a measurement of the whole board's power network. Zones, vias and trace/zone hybrids depend on actual filled connectivity and selected terminals. Refine the mesh and compare convergence. Reported source V/I differs from copper drop/I. Pulse/fusing risk is a screening estimate, not a fuse-opening or cooling simulation.
The mini console accepts pad references such as U8.2 and series branches such as L1.1 5mH+30m L1.2. See Quick PI command examples for complete commands, engineering units and DC/inductance limits.
Use Quick PI’s Decoupling placement tab to review capacitor distances and pad/rail topology. Its heuristics complement the DC solver; they do not simulate transient PDN impedance.
For connected RLC extraction, use explicit start/end pads or zone/plane terminals and verify stackup/reference assumptions. A result marked unknown or partial must remain so until the missing inputs or connectivity are resolved.
Quick SI also offers an optional Eye / step preview: a uniform lossless-line PRBS7 model using explicit bit rate, driver swing and resistive endpoints. It can illustrate ringing and sampled eye closure, but does not simulate IBIS drivers, coupled crosstalk or protocol compliance. See the model assumptions and CLI examples.
Quick SI can also assign vendor IBIS models to exact source and receiver pins and export complete selected routes as native KiCad simulation circuits. Copy circuit creates a retained model bundle and copies a flat circuit for pasting into Schematic Editor. The native KiCad simulator runs the IBIS models; the Eye / step preview above keeps its separate ideal model. See IBIS assignment, circuit export and limits.
QuickTherm spatial transients default to 0.1 s computed playback frames over a 10 s study. Set the solver maximum step and playback interval separately; use Previous/Next for individual frames or adjust playback speed. Large studies report storage limits rather than silently coarsening the requested interval.
Quick SI’s Return path tab retains transition/reference checks. Its Test points workflow exports test-point information and supports previewed net-name values and a silkscreen table. Review the selected set and proposed labels before writing; do not silently rename every footprint. Existing connector pin documentation remains in Pin Extractor.
For a quick placement screen, choose Quick 2D footprint screen on Mechanical Check’s Board page. Review same-side bounding-box warnings in its native canvas; the report remains INCOMPLETE because model height, enclosure and exact interference were not checked. Use Exact 3D mode with FreeCAD for those operations.
Copper Balancer’s preview explains region, density-ceiling and geometry rejections. Inspect the density range and remaining deficit before saving a new PCB copy; an already dense tile cannot be fixed by adding copper. Manufacturing Readiness compares board metrics to your actual fabricator profile. Neither tool replaces final native DRC and fabrication review.
Analytics Studio's primary workflow is open the originating project → edit fields → preview a component list → export. The three primary views are BOM workspace, Exports & templates, and Review & native sync. Select BOM, test points only or DNP only, then a template and grouped or individual rows. Exclude test points/DNP independently for BOM exports. Cell and bulk editing remain available; advanced tools are folded away. Native KiCad BOM settings can be inherited; advanced catalogue, variant and automation tools are optional. Save a workspace to retain the staged review. Exporting a BOM and applying native schematic edits are different operations.
Open Cost & mass to review component coverage and enter a bare-board mass or a material-volume estimate. PCB cost uses an explicit quote, setup charge, quantity and currency. Missing component values and mixed currencies keep combined totals unknown. Save the HTML/JSON/CSV report in the originating project's reports/wayricad-bom/ folder.
Use the magnetic designer for winding geometry and reduced core calculations. The separate two-winding coaxial FEM workflow extracts self/mutual inductance, coupling and short-circuit leakage, with field and mesh previews. Its explicit coaxial geometry is independent of the generated PCB winding. Supply winding resistance explicitly. Capacitance can be entered or computed in the separate geometry/dielectric workflow; inspect its terminal mapping and partial-coverage limits before use. Review B/H, model assumptions and the equivalent before exporting project-local HTML, JSON and SPICE files.
Magnetic reference checks and model boundaries explain independent magnetic/electrostatic field and KiCad ngspice validation. Motor models and research explain winding factors, phase topology, geometry-derived EMF and the small-motion model.
Embed3D consolidates library localization and model portability. Its default library folder is local/ inside the project, and the destination is editable. Resolve missing dependencies, review proposed copies/relinks, save and close project editors, then apply with backups. Missing external models are not generated automatically.
The current window shows the project-local folder, reviewed relinks and backup workflow.
Choose a balanced preset, inspect the logical coil connections, then review EMF/effort and phase events. Field and drive inputs are separated into tabs. The mechanics view runs KiCad SPICE with explicit ideal-current assumptions; export preserves plots, coil assignments, inputs and the circuit. Logical layouts are not manufactured copper geometry.
- No packages in PCM: use the raw
repo.jsonURL, select the repository and clear filters. Repository diagnostics. - Installed but no window: inspect the plugin environment/dependency error, then recreate the environment after fixing it. Launch diagnostics.
- Wrong or unavailable project: save the board, launch from its PCB Editor, and check the source path. Multiple Windows KiCad 10.0.5 editors may need separate temporary namespaces.
- Partial analysis: inspect missing stackup, terminals, filled zones, models or connectivity. Do not turn a partial result into a pass by suppressing the warning.
For a report, include the tool/version, OS, KiCad version, operation and redacted error text. Do not share IPC tokens. The Marble smoke record documents bounded checks and their remaining limitations.
Install Project Fusion 0.9.8 and Variant Manager 0.6.1 independently through PCM, then restart KiCad. Fusion guides source selection, variant destination, preview and offline Apply; Variant Manager handles the resulting native configurations.
If Fusion reports a failed preview or Apply, correct the reported source/settings and run a fresh Preview. Earlier review state is cleared. The Issues panel retains source repair choices and shows the latest failure with recovery guidance. Import and subsheet dialogs provide selectable details and Copy details.
Variant Manager keeps the previous staged batch after an ordinary staging error. If the saved source changed or Apply failed, export the retained review if needed, then reload and stage a new review. Apply remains blocked until then. Apply or clear a staged restore before adding ordinary batch operations. Report export failures leave the review available for another output path.
CLI: wayricad-fusion --help and wayricad-variants --help. Fusion exit code 3
means the operation completed but saving its result failed; the result is on
stdout. Inspect the result and backup before repeating a write. Always inspect
reported rollback failures and recovery backups before another Apply.
Open Silkscreen Label Placer, choose selected parts or the whole board, click Preview and inspect the top/bottom views. Apply only the accepted labels. Hidden/locked items stay untouched and unresolved placements remain listed. Options adds values or existing board text and sets size/spacing; distant component labels use checked guide lines. Run native DRC and inspect assembly readability before saving. The plugin guide covers installation and limits.
Layer Counter adds L1, L2 and subsequent physical copper-layer labels as a native group. Choose a style and copper layers, review Preview, then Add. Move the group with KiCad M; its multilayer zone-only keepout moves with it. Refill zones and inspect DRC/manufacturing plots. Core styles require explicit adjacent layer pairs from your fabrication stackup.
Component Arranger adds a guided group/anchor/area workflow. It supports rotation, top/bottom choices, requested density and capacitor ordering. Preview is read-only; locked/routed footprints stay fixed, and native DRC/connectivity gates Apply. See its guide for wire-cluster label confirmation, CLI, package limits and the meaning of its ratsnest proxy.