microwind

Simulation projects on VLSI design.

Here Digital IC Design Lab topics are covered to meet OU syllabus.

This repo contains the lab files for my CSE460: VLSI course at BracU, written in VHDL, DHCP and MicroWind.

Microwind design files for an XNOR gate submitted as the final project to ORION SEMICONDUCTORS' 2026 summer internship for physical design

VLSI Circuits Design Laboratory works using DSCH2 and Microwind2

In this repository, there are designs and simulations for VLSI chip projects based on simple CMOS logic circuits and gates, created using the Microwind tool.

This repository contains various VLSI Design LAB experiments created DSCH,Microwind and Icarus Verilog (4th Year, 1st Semester) at MBSTU.

A useful Python script generated by Claude for generating a power grid for Microwind.

Transistor-level design, simulation, and layout of a 2-bit Vedic multiplier using CMOS technology with netlist and layout optimization.

This project demonstrates the design and implementation of a Boolean expression using PMOS-only transistors in Microwind. It includes Boolean simplification, gate-level design, transistor-level schematic, stick diagram, Microwind layout, and simulation analysis with results and comparisons to CMOS

CSE4218 VLSI Design Lab Materials Notes and Lab works

This repository contains all of my lab work for the course CMOS at IIITN.

CMOS NAND-based smart food packaging circuit designed in MicroWind and verified through SPICE/PSpice simulation and waveform analysis.

this repo contain simulations of various circuits

Custom CMOS logic gate physical design using Microwind, including stick diagram, layout implementation, and functional verification.

A practical Introduction to simulation software's

This project showcases the design and simulation of a 7T MCPL SRAM using adiabatic logic for low-power efficiency, developed for ECL 312 at IIIT Nagpur. It compares the 6T and 7T SRAM designs in terms of power, energy, and stability, with simulations done in WinSpice and Microwind.

These are the lab exercises of the VLSI Lab of CEID

This project showcases the design and simulation of a 2-Bit CMOS Comparator, developed for ECL 312 at IIIT Nagpur. It consists of results of simulations done in WinSpice and Microwind.