CMOS Logic Gate Physical Design using Microwind

Overview

This project demonstrates the custom CMOS implementation of the Boolean function

K = (X + YZ) + (AB + C(D + E))

using Microwind. The design includes transistor-level CMOS implementation, stick diagram development, physical layout creation, and functional verification through transient simulation.

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Boolean Function

K = (X + YZ) + (AB + C(D + E))

Equivalent form:

K = X + YZ + AB + CD + CE

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Design Flow

Boolean Function
      │
      ▼
CMOS Transistor Design
      │
      ▼
Stick Diagram
      │
      ▼
Physical Layout
      │
      ▼
Simulation & Verification

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Results

Stick Diagram

The stick diagram illustrates the transistor placement and routing strategy used before physical layout implementation.

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CMOS Physical Layout

The CMOS layout was implemented in Microwind following λ-based design rules.

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Simulation Results

Transient simulation confirms the correct functionality of the implemented CMOS logic.

Tools Used

• Microwind
• CMOS Technology Library (1.2 V)

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Repository Structure

CMOS-Logic-Gate-Physical-Design/
│
├── README.md
├── REPORT.md
├── LICENSE
├── .gitignore
├── cmos_logic_gate_layout.msk
└── images/
    ├── stick_diagram.png
    ├── microwind_layout.png
    ├── simulation_waveform.png

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Author

Samyak Shah

B.Tech Electronics and Communication Engineering
Institute of Technology, Nirma University

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License

This project is licensed under the MIT License.