# VERILOG_CODES

This repository contains Verilog HDL practice codes developed during my VLSI training and self-practice period.

It includes combinational, sequential, and behavioural modeling examples with corresponding testbenches, waveforms, and schematics.

## Contents

- Combinational Logic Designs

- Sequential Logic Designs

- Behavioural Modeling Practice

- RTL Design Fundamentals

## Folder Structure

VERILOG_CODES

├── RTL_Design_Basics

│ ├── src

│ ├── testbench

│ ├── waveforms

│ └── schematic

│

├── BEHAVIOURAL_MODEL

│ └── (Institute training practice codes)

│

└── README.md

## Tools & Skills Used

- Verilog HDL

- RTL & Behavioural Modeling

- Digital Logic Design

- Testbench Development

- Simulation & Debugging

## Purpose

This repository is maintained as part of my **VLSI design training practice** to strengthen RTL coding and verification fundamentals.

## Author

**B Gowrish**

B.E. Electronics & Communication Engineering (2025)

CGPA: 8.14

VLSI Design & Verification Trainee – VLSI 1st, Bengaluru