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  • VLSI 1st Institute
  • Bengaluru
  • 10:22 (UTC -12:00)
  • LinkedIn in/gowrish289

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gowrivlsi/README.md

💫 About Me:

🔭Electronics & Communication Engineering student specializing in VLSI Design and Verification with strong interest in RTL Design and UVM-based verification.

Currently undergoing professional VLSI training at VLSI 1st, Bengaluru, gaining hands-on experience in Verilog, SystemVerilog, UVM, simulation, and digital design methodologies.

B.E. in Electronics & Communication Engineering (2021–2025) | CGPA: 8.14

Actively building and sharing projects related to RTL development, functional verification, and chip design. I’m currently working on
👯 I’m looking to collaborate on
🤝 I’m looking for help with
🌱 I’m currently learning
💬 Ask me about
⚡ Fun fact

🌐 Socials:

LinkedIn email

💻 Tech Stack:

C

📊 GitHub Stats:



🔝 Top Contributed Repo

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  1. VERILOG_CODES VERILOG_CODES Public

    Verilog HDL practice repository containing combinational, sequential, and behavioural design examples developed during VLSI training, with testbenches, waveforms, and schematics.

    Verilog

  2. gowrivlsi gowrivlsi Public

    Electronics & Communication Engineering student specializing in VLSI Design & Verification with strong interest in RTL & UVM. Currently training at VLSI 1st, Bengaluru with hands-on experience in V…

  3. VERILOG_CODES_PROJECTS VERILOG_CODES_PROJECTS Public

    Collection of RTL and Verilog projects including FIFO designs, FSM systems, parameterized RAM, and PCIe SERDES implementation with testbenches, waveforms, and schematics.

    Verilog