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Add vec4 gemm! - #7

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haixuanTao wants to merge 2 commits into
dimforge:mainfrom
haixuanTao:feat/gemm-vec4
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haixuanTao wants to merge 2 commits into
dimforge:mainfrom
haixuanTao:feat/gemm-vec4

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@haixuanTao

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Two vec4 changes to the tiled GEMM, both verified bit-exact (0.0) vs the
scalar gemm_tiled:

  • gemm_tiled inner loop now does 4-wide vec4 FMAs (acc: [Vec4;4],
    bvec.mul_add(Vec4::splat(a), acc)) instead of 16 scalar MACs.
  • new gemm_tiled_vec4 shader + Gemm::dispatch_tiled_vec4 host: loads the
    A/B tiles from global memory with 128-bit vec4 transactions (host
    reinterprets the buffers as glamx::Vec4). Assumes contiguous row-major,
    single batch, and tile-filling dims (M%64, N%64, K%16); the host falls
    back to scalar gemm_tiled for transposed/odd-dim cases.

Pulls in glamx. Measured on an RTX 5090: the compute-FMA vec4 is ~+12%
(rust-gpu -> SPIR-V -> NVIDIA does not auto-vectorize the inner loop the
way Metal does); the vec4 global loads are ~+0% because a tiled GEMM
already amortizes global memory (load once into smem, reuse), so it is
not bandwidth-bound. Lesson: for a tiled GEMM, vec4 the compute, not the
global loads.

haixuanTao and others added 2 commits May 26, 2026 16:20
Adds vortx::linalg::{Activation (tanh + tanh_backward), Adam} and their shaders,
the GPU building blocks for MLP training (used by nexus RL demos / zealot-rl).

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
Two vec4 changes to the tiled GEMM, both verified bit-exact (0.0) vs the
scalar gemm_tiled:

- gemm_tiled inner loop now does 4-wide vec4 FMAs (acc: [Vec4;4],
  bvec.mul_add(Vec4::splat(a), acc)) instead of 16 scalar MACs.
- new gemm_tiled_vec4 shader + Gemm::dispatch_tiled_vec4 host: loads the
  A/B tiles from global memory with 128-bit vec4 transactions (host
  reinterprets the buffers as glamx::Vec4). Assumes contiguous row-major,
  single batch, and tile-filling dims (M%64, N%64, K%16); the host falls
  back to scalar gemm_tiled for transposed/odd-dim cases.

Pulls in glamx. Measured on an RTX 5090: the compute-FMA vec4 is ~+12%
(rust-gpu -> SPIR-V -> NVIDIA does not auto-vectorize the inner loop the
way Metal does); the vec4 *global* loads are ~+0% because a tiled GEMM
already amortizes global memory (load once into smem, reuse), so it is
not bandwidth-bound. Lesson: for a tiled GEMM, vec4 the compute, not the
global loads.

Note: the one-line glamx Cargo.toml dependency is shared with the ELU and
PPO-kernels branches; whichever lands first, the others need a trivial
rebase of that line.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
@sebcrozet

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This is being merged as part of #11

sebcrozet added a commit that referenced this pull request Aug 27, 2026
* feat: move inferi shaders into an optional ml module for vortx

* chore: cargo fmt

* feat(ml): add tanh activation + Adam optimizer GPU ops

Replaces #5

Co-Authored-By: Haixuan Xavier Tao <tao.xavier@outlook.com>

* refactor(ml): move the tanh-backward + Adam kernels into vortx::ml and drop the duplicated tanh forward

Completes #5

* feat(ml): add ELU activation GPU ops (fwd/backward/vec4)

Replaces #6

Co-Authored-By: Haixuan Xavier Tao <tao.xavier@outlook.com>

* refactor(ml): keep only the ELU backward pass, the forward is already UnaryOp::Elu

Completes #6

* feat(ml): add PPO loss-gradient GPU kernels

Replaces #5

Co-Authored-By: Haixuan Xavier Tao <tao.xavier@outlook.com>

* refactor(ml): wire the PPO kernels to vortx::ml and use StepRng for uniform control flow

Completes #5

* perf(linalg): vec4 GEMM (compute-FMA inner loop + vec4 global-load variant)

Replaces #7

Co-Authored-By: Haixuan Xavier Tao <tao.xavier@outlook.com>

* perf(linalg): keep the vec4 FMA inner loop, drop the unmeasured vec4 global-load GEMM variant

Completes #7

* feat(ml): gpu_ppo_stage_batch, building the PPO minibatch on device

* chore(ml): comment cleanups

* chore: CI fixes

---------

Co-authored-by: Haixuan Xavier Tao <tao.xavier@outlook.com>
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2 participants