Repository navigation
arm64: dts: apple: t8142: system level cache (MCC) node, enabled on J815 - #1567
Conversation
RyanTheTide
left a comment
RyanTheTide
left a comment
There was a problem hiding this comment.
The node follows the T8140 layout and binding, and the J815 log shows all four planes. Approved once CI has run.
|
@m0d16l14n1 dt-checks adds 3 warnings: apple,t8142-mcc isn't in the MCC binding (compatible oneOf fails, and 'reg' is unevaluated) on t8142-j704 and t8142-j815. Please add apple,t8142-mcc to the binding (or use the existing fallback compatible) so dt-checks passes, then we'll merge it. |
M5 (T8142) has the T8140 system level cache register layout (ways 0x2800, power 0x2804, allocation disable 0x82c, flush 0x2844) at T8140's offsets, so it falls back to apple,t8140-mcc. List it in the select and with T6041 as a compatible that takes the apple,t8140-mcc fallback. Assisted-by: Claude Opus 5.5 Signed-off-by: Nick <nekreshen@yandex.ru>
Four SLC planes 0x40000 apart from ADT mcc reg[1], T8140's register layout. Disabled in t8142.dtsi, enabled on J815. The boot loader (aura, mcc_init_m5 from m1n1) turns allocation on; the driver checks the ways and power state and flushes on shutdown. Tested on J815: "apple-mcc 220000000.memory-controller: system level cache allocation enabled on 4 planes". Assisted-by: Claude Opus 5.5 Signed-off-by: Nick <nekreshen@yandex.ru>
a09c7a9 to
167e403
Compare
|
@RyanTheTide Thanks. |
RyanTheTide
left a comment
RyanTheTide
left a comment
There was a problem hiding this comment.
Binding update checked: apple,t8142-mcc now validates with the t8140 fallback and dt-checks passes on j704/j815. The DT node is unchanged.
429e727
into
aurora-silicon:integration/aurora
Describes the M5 (T8142) system level cache controller, so
apple-mcccan confirm it and flush it on shutdown.apple,t8142-mccwith theapple,t8140-mccfallback. T8142 has T8140's register layout at T8140's offsets (ways 0x2800, power 0x2804, allocation disable 0x82c, flush 0x2844), so no driver change.memory-controller@220000000, four planes 0x40000 apart, from ADTmccreg[1] (amcc-reg-idx 1, one AMCC, amcc-plane-enable-mask 0xf). Disabled by default.The boot loader already turns the cache on: m1n1 has T8142 support (AsahiLinux/m1n1@578600a1, Sven Peter) and aura carries it as cc71e04c
mcc_init_m5(). The driver only checks the ways and power state, re-clears the allocation-disable bit and flushes on shutdown; a plane that isn't ready gets a warning and is left alone.Tested on J815 (MacBook Air 15-inch M5, aura Stage 2):
apple-mcc 220000000.memory-controller: system level cache allocation enabled on 4 planes.DTBs build without DTC warnings on this base.
Notes:
apple,t8142-error-handlernode int8142-peripherals.dtsialso maps 0x220000000 (+0x140000). That's harmless while it stays disabled; enabling it later would need the MCC window carved out.t8142.dtsion this base, so it is unaffected. Once it does (arm64: dts: apple: MacBook Air 15-inch M5 (J815) device tree #1532), a J813 owner can enable&mccafter the same one-line dmesg check.Part of the J815 bring-up; board results are summarised in discussion #135.
Assisted-by: Claude Opus 5.5