[joske]

The M4 Max laptops run their three USB-C ports at USB 2 only:

• the PHYs carry a hardcoded USB 2 tunable;
• the controllers are limited to high-speed, with only their USB 2 PHY;
• nothing connects the connectors' SuperSpeed lanes.

That's because the loader had no ATC tunables to give them. aurora-silicon/aura#147 exports them from the ADT on the J614c and J616c, as it already does on the J614s. With that in place, this PR describes the ports the way the M4 Pro does.

arm64: dts: apple: t6041-j614c-j616c: enable USB 3 on the USB-C ports

• The controllers use both PHYs. The PHYs link to the connectors' SuperSpeed lanes and to the controllers.
• The PHY mailboxes are on.
• The hardcoded ATC and controller tunables are dropped. This includes the full set the USB-C DisplayPort description added to atcphy1. The loader appends its own, so leaving them would duplicate every entry.
• The HDMI PHY keeps its tunables.

soc: apple: display-gate: leave the M4 Max ATC1 mailbox to the PHY
The M4 Max USB-C display chain listed atcphy1's mailbox among the nodes it enables. With the mailbox on for USB 3, the gate refused to bring up dcpext1:

apple-t6041-display: /mailbox@38b148000: already enabled, nothing changed

The mailbox belongs to the PHY coprocessor, so this drops it from the chain, as the M4 Pro's chain leaves its ATC mailboxes out. It's also marked enabled in the KUnit fixture.

This builds on #1468, which adds the left-back port. It needs the aura change above: a loader without it leaves these PHYs with no tunables, and the ports don't work. It merges cleanly with #1472 and #1473.

Tested on a J614c (linux-aurora 28.5 with this, #1468, #1472, #1473 and the #1475 PHY fix; aura with the change above):

• USB 3: a Samsung T7 Shield runs at SuperSpeed Plus Gen 2x1 (10 Gbps) on all three ports, in both plug orientations, with 663 MB/s sequential reads. A DisplayLink dock now enumerates at 5 Gbps.
• Display gate: it enables /dcp@602e00000 with the mailbox already on. USB-C DisplayPort works on the left-front port, as does HDMI.
• Switching: DisplayPort and USB 3 alternate on the left-front port. Going from DP to USB 3 relies on the PHY fix, phy: apple: t6040: put the PHY to sleep when four-lane DP ends #1475.

Not tested on the J616c.

🤖 Generated with Claude Code

[DjDeveloperr]

Codex (GPT-6.1 Sol), reviewing on @DjDeveloperr’s behalf.

No remaining blocking source findings in the reviewed/integrated net change. Integration preserves the now-merged1468port graph and1475DP-to-USB3 PHY teardown. Matching Aura147 must also land for the source pair; no old-loader default rollout is approved. The mailbox is removed from the shared max-chain array, and1546 has a corresponding fix candidate so it cannot skip the crossbar. Original ancestry and newer main behavior retained; fresh native/host/DT gates are required before merge.

Approval does not waive pending CI, dependency order, hardware-safety gates or source-versus-release qualification. No source merge is an installed-loader write or a new hardware test.

[DjDeveloperr]

Codex (GPT-6.1 Sol), reviewing on @DjDeveloperr’s behalf.

The source failure was reproduced on the exact CI base290571a: refkey.rs and test_policy_window.py are byte-identical to the failed head67c6c636. The check reads only the text before PREPARE inside a deferred closure and misses the later real-root policy_window(unlock) dispatch. Guarded initrd remains read-only and the write-refusal check remains intact; no production guard change is warranted.

Appended test-only48bf7a41 and opened shared fix #1564. The exception is limited to refkey_unseal_cached: PREPARE must be inside its named closure, the direct invocation must be in the existing keystore_only branch, the real-root invocation must use policy_window, and all closure uses are counted. Existing call-site/Touch ID assertions remain. Seven cases pass normally and with Python -O; mutants removing the real-root wrapper or adding an unguarded call are rejected. Independent review also rejected reversed-condition and out-of-closure cases. All42 production Rust files match the tested integration fixture exactly.

No M4 driver/DT/loader or SEP policy changed. Source approval is retained; fresh host/DT/SEP checks on48bf7a41 and the1472->1473->1476 merge order plus Aura147 pairing remain required. Do not retry the superseded old source failure.