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arm64: dts: apple: describe disabled M1 Pro, Max and Ultra resources - #1157
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Describe additional codec, DMA, display, crypto and auxiliary SPMI resources without enabling them. Reuse integrated schemas and preserve the existing device state. Leave reference-Mac SPI4 and base SPMI controller ownership with the separate board audit. Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com> Assisted-by: LLM
Keep primary PMIC bus operations unchanged and describe the separate disabled interrupt monitor and battery function. Retain the Studio hub firmware flash on its native single chip select without firmware contents. Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com> Assisted-by: LLM
Split aggregate cache/error/event descriptions onto the physical die buses and retain global registerless clock selectors at the root. Bind each qualified die layout without changing existing enabled devices. Correct singleton schema arrays. Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com> Assisted-by: LLM
Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com> Assisted-by: LLM
Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com> Assisted-by: LLM
All six T600x board ADTs place the primary encoder and its two DARTs in the 0x40d region. Retain their disabled state while correcting the physical addresses and unit names. Drop the last dangling include of the waived CPU debug description. Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com> Assisted-by: LLM
…CI ranges Retain the existing secondary-ANE PMGR register descriptions as disabled providers so the disabled consumers resolve without enabling power states. Decode each PCI range as little-endian 64-bit address/length pairs before encoding the standard DT cells and translating the parent through its owning die. Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com> Assisted-by: LLM
Preserve the integrated eight-register display layout while allowing the seven-register M1 extra-controller auxiliary aperture at its native position. No other task branch is merged. Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com> Assisted-by: LLM
Import only the current integration base, including the merged reference-board descriptions; no task branch is merged. Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com> Assisted-by: LLM
Extend the merged auxiliary SPMI controllers with their native windows and event domains, PMIC/radio/NFC followers and first-generation panel controls. Share portable controls only with the M1 board family and retain existing reference-board ownership. Keep timer PWM separate from the overlapping FPWM view, and constrain the driverless secondary ANE schema independently of existing ANE layouts. Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com> Assisted-by: LLM
…pendently Keep all existing generation constraints while describing the secondary instance with its one system CPU domain and four native clock selectors. Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com> Assisted-by: LLM
Put the native SPI4 selector beside its populated portable clients. Preserve unused desktop controller defaults, and document the secondary ANE four-clock resource form. Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com> Assisted-by: LLM
Sort and retain every compatible from both sides. Preserve the distinct M1/M3 register cardinalities, dual-bank T6000 AES mapping, optional M3 scaler resources and existing AVE named layouts. Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com> Assisted-by: LLM
Keep sorted compatible unions, M1 dual-DART AES, per-generation scaler domains and the distinct AVE register-name forms without dropping integrated resource shapes. Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com> Assisted-by: LLM
Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com> Assisted-by: LLM
Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com> Assisted-by: LLM
The intervening AVD driver update leaves DT, binding and DTC inputs unchanged. Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com> Assisted-by: LLM
Retain the sorted SD-control compatible union and the single PMIC event definition. Other integrated M1 binding resolutions are identical. Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com> Assisted-by: LLM
RyanTheTide
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November 7, 2026 18:18
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DT train check (DT3), merge of head 98fa38b into integration/aurora 72b828e (after #1166): apple-dt-check.sh W=1, 122/122 DTBs, make rc=0/0, 443/443 inherited warning lines, new warnings: 0, removed: 0; 11/11 touched bindings ok; 0 new status = "okay" lines. Describe-only, ready for the merge train. |
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Brings aurora-wip up to the 11-08 morning integration tip: DT descriptions for every Mac family (#1094, #1097, #1111, #1131, #1132, #1148, #1149, #1155, #1156, #1157, #1172), the J616s scaler (#1168), the panel primaries from boot data (#1105), AVD macOS command parity (#1116), AVD dma-coherent (#1169), the M2 PMU RTC alarm (#1151), G17 admission without spinning (#1146) and the AOP map wait (#1147). Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com> Assisted-by: LLM
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M1 Pro, Max and Ultra trees omit codec/DMA, extra-display, crypto, PMIC, NFC and panel-control resources. Describe them with integrated generic bindings and native die translations. Correct the existing disabled primary AVE and DART windows to the physical 0x40d region, split Ultra aggregate cache/error/event records per die, and keep timer PWM distinct from FPWM. Every newly added node is explicitly disabled.
This supersedes #1121. The branch began directly on integration and incorporates only subsequent integration updates, including final #1112 and merged #1094. Its disabled base SPI4/SPMI controllers are reused and extended; reference-board motion and existing PMIC details remain intact. M1 portable controls are shared behind a family guard because their parent include is also used by M2. The J316s board file is unchanged. Firmware-only/debug/trace views are waived in external ledgers; no firmware, calibration, callback programs or audit documents are included.
Validation at head
98fa38b5314e, independently merged onto integrationd1aee193d36b, on the buildbox through the permitted normal-slot interactive path (controller confirmationh-50514running):9f586331dfd7, W=1, eight jobs: 122/122 base/head DTBs build, 0 new / 0 removed warnings, all 11 remaining touched bindings report binding ok. The 600 inherited warning lines and existing catalog decoder exceptions remain unchanged.d1aee193, after arm64: dts: apple: describe disabled T8103 hardware resources #1156 landed. Shared binding compatible lists are sorted unions of M1/M2/M3 variants; resource cardinalities and AVE names from every side are retained. The single PMIC event definition is checked after the automatic merge.The current-tip required check returned rc 0; complete stream/source proof is retained in ci/t-5541/d1-t600x-interactive.log and the task-owned buildbox tree. Static descriptions are ready for DT2 review. No board was boot-tested; secondary engines, routes, clock/transport backends and firmware ownership remain unqualified. Enables belong in separate PRs. Per-node source paths remain in the external DT-GAPS ledgers.