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arm64: dts: apple: describe disabled T602x resources on merged bindings - #1149
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Describe the M2 Pro, Max and Ultra media, display, DMA, cache and SPMI resource topology. Preserve die bus translation and interrupt selectors, and correct the copied I2C register addresses. Keep all new controllers disabled pending driver and ownership qualification. Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com> Assisted-by: LLM
Drop the inherited SIO alias addition from this describe-only series. Adding a loader alias enables the controller at boot and needs separate qualification. Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com> Assisted-by: LLM
The firmware audio interface retains its existing PMGR reset-domain phandle. Declare its phandle-array type so schema assembly can decode the property. Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com> Assisted-by: LLM
Later-generation AOP nodes advertise a T6020 transport fallback but use different service compatible lists. Select this binding only for the single-compatible M2 nodes so it does not impose M2 service contracts on those later generations. Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com> Assisted-by: LLM
The fourth PCIe-C host on each die has the same register, interrupt and MSI layout as the existing T602x template. Keep its Ultra tunnel, host and DART disabled. Reuse these canonical DART nodes for PIODMA instead of describing duplicate register banks at the die root. No loader aliases or link enablement are added. Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com> Assisted-by: LLM
The expanded register audit identifies a different LTSSM aperture on the disabled Ultra fourth hosts. Retain the original Pro/Max form and describe the Ultra register list independently from its hardware inventory. Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com> Assisted-by: LLM
The expanded 42-host audit finds the same copied LTSSM address discrepancy in every T602x template instance. Describe the native apertures for Pro, Max and Ultra and remove the unnecessary fourth-host register-form split. No enablement or aliases change. Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com> Assisted-by: LLM
… cases Preserve the merged DCP exceptions and NVMEM devices while retaining M2 disabled resource forms. Remove duplicate auto-merged T8112 SPI/SPMI enum entries. Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com> Assisted-by: LLM
…dress ranges Describe the new Ultra logical bus windows with an address-qualified node name and identity translations for controller/config and downstream PCIe memory apertures. This fixes the new simple_bus_reg W=1 diagnostics while preserving child addresses, disabled state and existing Pro/Max paths. Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com> Assisted-by: LLM
Union and sort shared compatible entries, preserve merged M3 and legacy contracts, and constrain AES, scaler, AVE and ProRes layouts per generation. Keep reference-Mac descriptions unchanged. Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com> Assisted-by: LLM
RyanTheTide
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November 7, 2026 17:39
integration/aurora already lists every T602x compatible in the eleven shared bindings that conflicted (aes, dpin, pciec-piodma, soc-error-handler, jpeg, prores, scaler, t8140-ave, pwm, dwi, t8140-mcc), with its later per-generation conditions, so those files take the integration side unchanged. Device tree sources merged without conflicts. Assisted-by: LLM Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com>
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DT train (DT3): merged integration/aurora 3e82213 (after #1157) into this branch as 9c9aaaa. The eleven conflicting shared bindings take the integration side, which already lists every T602x compatible. The merge leaves DTS-only changes against the tip (19 files, 0 binding files). apple-dt-check.sh on the merge: W=1, 122/122 DTBs, make rc=0/0, 443/443 inherited warning lines, new warnings: 0, removed: 0; 0 new status = "okay" lines. pmic@f -> pmic@b is a node rename only (reg 0x0b on both sides). |
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Retain the describe-only fleet additions on the #1149 integration tip. No driver changes, new enables or CPU idle-state links are added relative to integration. Assisted-by: LLM Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com>
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Brings aurora-wip up to the 11-08 morning integration tip: DT descriptions for every Mac family (#1094, #1097, #1111, #1131, #1132, #1148, #1149, #1155, #1156, #1157, #1172), the J616s scaler (#1168), the panel primaries from boot data (#1105), AVD macOS command parity (#1116), AVD dma-coherent (#1169), the M2 PMU RTC alarm (#1151), G17 admission without spinning (#1146) and the AOP map wait (#1147). Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com> Assisted-by: LLM
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Describe missing M2 Pro/Max/Ultra media, DMA, SPMI and second-die resources. Complete disabled Ultra fourth PCIe-C hosts with canonical DARTs and identity ranges covering controller/config and downstream PCIe memory windows. Correct copied I2C windows, PMIC unit naming and PCIe-C LTSSM apertures. Existing Pro/Max paths are retained; no loader alias or link enablement is added.
Current head 4f0951b.
Verified by controller buildbox h-50458, completed rc=0, using the original full-catalog apple-dt-check.sh (SHA-256 9f586331dfd7) as explicit merges into integration 95e30d5:
Compatible enums are the sorted M2/M3 union. AES/scaler/AVE/ProRes constraints retain generation-specific layouts and the existing legacy cases. Integration 95e30d5 is merged with ordinary merge commits, no force push. #1094 reference-Mac descriptions and canonical labels are retained; J413/J316s board files are unchanged from that integration source. New controllers remain disabled; firmware/debug endpoints are waived. No target boot/peripheral qualification is claimed. Audit/private inputs stay outside the kernel repository. Baseline catalog diagnostics remain; the comparison introduces none.
Replaces #1119. Generic contracts are shared with #1148.
Supplementary audit of the exact verified DTBs passes rc=0: 290/290 register/IRQ/applicable IOMMU facts, canonical controllers and disabled Vale PMICs, complete Ultra host register/PCIe-memory translations, and zero selected vendor-contract diagnostics across 194 collected SoC DTBs. The required full-catalog check above is unchanged.