Sovereign silicon for the AI era — five chips, one SDK, one engineering discipline.
We design five category-defining silicon products from the transistor up.
Datacenter AI · Rad-hard space · Sub-THz 6G · Crypto & ZKP · Healthcare-native.
Architecture, RTL, verification, compiler, runtime, SDK — one team, one portfolio, one mission.
Website · Developer Docs · SDK Examples · v0.2.0 Release
Zhilicon's five silicon products are purpose-built for verticals where incumbent AI silicon cannot credibly serve regulated buyers. Each has its own category; the SDK spans them all.
| Chip | Category | Target |
|---|---|---|
| Discovery-1 | Healthcare-native AI — DICOM ASIC, privacy enclave, FDA 510(k) pathway | Q3 2026 tape-out |
| Horizon-1 | Rad-hard space AI — 300 krad TID, TMR-protected 16.4 TOPS, DO-254 DAL-B | Q1 2027 tape-out |
| Nexus-1 | Sub-THz 6G — D-band hybrid-bond GaN/CMOS, on-die AI-learned beamforming | Q4 2026 Rev A |
| Sentinel-1 | Crypto & ZKP — FIPS 140-3 L4 + silicon ZKP engines + silicon PQC | Q2 2026 tape-out |
| Prometheus | Datacenter AI — 8-chiplet X-Cube SoIC-X, dual-foundry (Intel 18A + Samsung SF2) | Q3 2026 tape-out |
Every chip is category-creating, not a spec-sheet comparator.
Zhilicon owns every layer — from silicon architecture to the Python SDK you pip install. Every layer ships from this organization.
┌───────────────────────────────────────────────────┐
│ │
Developer Surface │ SDK Examples · Benchmarks · Developer Docs │
│ (public — start here) │
│ │
══════════════════════╪═══════════════════════════════════════════════════
│ │
Software Stack │ Python SDK · Compiler · Runtime · Boot FW │
│ 5 chip packages · ONNX · HuggingFace · Chat API │
│ │
══════════════════════╪═══════════════════════════════════════════════════
│ │
Silicon │ Architecture · Microarchitecture · RTL │
│ UVM Verification · Verification Plan │
│ │
└───────────────────────────────────────────────────┘
│
┌─────────┬─────────┬──┴───────┬──────────┬──────────┐
│Discovery│ Horizon │ Nexus │ Sentinel │Prometheus│
│ -1 │ -1 │ -1 │ -1 │ │
└─────────┴─────────┴──────────┴──────────┴──────────┘
No hardware needed. The full SDK runs on a pure-numpy emulation backend.
git clone https://github.com/zhilicon-ai/zhilicon-sdk-examples.git
cd zhilicon-sdk-examples
pip install git+https://github.com/zhilicon-ai/zhilicon-sdk.git
python demos/leo-satellite-inference/demo.pyExpected output in under one second:
========================================================================
ZHILICON LEO SATELLITE DEPLOYMENT EVALUATION
========================================================================
[1/5] ✓ SOVEREIGN ZONE ae-defense-leo (classified)
[2/5] ✓ CHIPLET FABRIC 8 chiplets, max-abs-diff 0.00e+00 vs single-chip
[3/5] ✓ RAD-HARD SEU CAMPAIGN FIT/Mbit 560 (< 1000 unhardened reference)
[4/5] ✓ 6G DOWNLINK (140 GHz) +13.9 dB SNR, 9.32 Gbps @ 500 km
[5/5] ✓ CRYPTO ATTESTATION HMAC-DRBG key + TVLA PASS + signed receipt
OVERALL: ALL FIVE CHECKS PASSED
One script, four chips composed, deterministic output, 428 passing tests back it. "One API, five capabilities" — runnable today, pre-silicon.
Released 2026-04-18. First production drop of the five-chip mitigation sweep. Full release notes.
| Package | Chip | Closes audit gap |
|---|---|---|
zhilicon.crypto |
Sentinel-1 | NIST SP 800-90A HMAC-DRBG + TVLA side-channel + CAVP generator |
zhilicon.medical |
Discovery-1 | HIPAA Safe Harbor 18-identifier scrubber + HMAC-chained audit log |
zhilicon.chiplet |
Prometheus | 8-chiplet fabric + tensor-parallel LLaMA (bit-identical to single-chip) |
zhilicon.rad_hard |
Horizon-1 | SEU injection (SBU/MCU/dist/BER) + TMR voter + robustness harness |
zhilicon.rf |
Nexus-1 | Friis link budget + MIMO channel + DFT/SVD/AI beamforming + OFDM |
428 tests passing across a Python 3.10 / 3.11 / 3.12 CI matrix. 29 ADRs documenting every silicon and SDK decision from first principles.
| Repository | Description |
|---|---|
zhilicon-sdk |
Python SDK v0.2.0 — five chip packages + serving + sovereign attestation |
zhilicon-sdk-examples |
Runnable demos — LEO cross-chip, sovereign inference on K8s, chat UI, CUDA migration |
zhilicon-developer-docs |
Public documentation site + 29 ADRs |
zhilicon-benchmarks |
Performance benchmark evidence (activates at first silicon) |
| Repository | Description |
|---|---|
zhilicon-compiler |
ZCC (Z Compute Compiler) — graph IR + MLIR dialect + codegen |
zhilicon-runtime |
ZRT on-device runtime + ZCCL collectives + Kubernetes operator |
zhilicon-boot-fw |
Boot firmware + secure-boot chain + SoC-level tools |
| Repository | Description |
|---|---|
zhilicon-architecture |
Per-chip architecture deep-dives + system block diagrams |
zhilicon-microarchitecture |
Per-chip microarchitecture workbooks + remediation |
zhilicon-rtl-top |
Top-level RTL sources for all five chips |
zhilicon-uvm |
UVM testbenches + cocotb harnesses |
zhilicon-verification-plan |
Verification closure + formal-proof tracking (5,442-property plan) |
| Repository | Description |
|---|---|
zhilicon-requirements |
Per-chip specifications + upgrade plans + ZPAS schemas |
zhilicon-release-management |
KPI dashboards + deliverables + spec-tools CI |
zhilicon-docs-internal |
Strategy, portfolio KPIs, board materials (Confidential — LP + Board only) |
- 29 Architecture Decision Records — every silicon and SDK decision documented with context, alternatives considered, and consequences.
- 428 SDK tests passing on every push across Python 3.10 / 3.11 / 3.12 matrix.
- Test-count regression guard in CI — silent test deletion is caught before merge.
- Dual-foundry production — Intel 18A + Samsung SF2 for Prometheus with an 8-week switch playbook.
- 5,442-property formal verification plan across the portfolio.
- Sovereign attestation at silicon level — per-zone data residency enforced in hardware (v2, post-silicon) and in software today (v1, ADR-0024).
- Contribute — See each public repo's
CONTRIBUTING.md. DCO sign-off required. - Issues — Use GitHub Issues on the relevant repository.
- Security — Report vulnerabilities privately per each repo's
SECURITY.md. - Community — Zhilicon on GitHub · zhilicon.ai.
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