Evaluate/support new ASAP7 6-track library

[harrisonliew]

https://github.com/The-OpenROAD-Project/asap7/tree/master/asap7sc6t_26 added on Oct. 15, 2021

[Waxpple]

Have we evaluated the new asap7 version 28?

[harrisonliew]

No, we have not yet. PRs are welcome!

[Waxpple]

@harrisonliew
Done. Please review the PR #673 and let me know if it is not working.
I have tested it.

[Waxpple]

There are some fixes in the newer version:

1. ICG lib with "clock gating function and state table" has been fixed. Question related to M5, M6 spacing? The-OpenROAD-Project/asap7#3
   Edit: ICG*DC* cells with incorrect width has been fixed. DRC error regarding fin The-OpenROAD-Project/asap7#12
2. Large ASNYC FF delay has been fixed. layout editor crashes upon opening any asap7_TechLib ivpcell crash The-OpenROAD-Project/asap7#9
3. Multi-VT GDS files missing has been fixed.

One known issue

1. Missing prefix in Verilog module name. Getting New LVS/DRC/PEX rule sets The-OpenROAD-Project/asap7#33

[Waxpple]

Also, I think somehow the timing library in version 27 caused the simulation to fail with a timeout. Still verifying this theory.