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An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Scala 2.4k 918
An open framework for designing and deploying custom AI-driven HW/SW co-design flows fast
Python 90 19
Berkeley's Spatial Array Generator
Scala 1.5k 294
Hammer: Highly Agile Masks Made Effortlessly from RTL
Python 325 80
chisel tutorial exercises and answers
Scala 757 195
A Heterogeneous GPU Platform for AI and Neural Graphics
Scala 67 5
Primary Git Repository for the Zephyr Project. Zephyr is a new generation, scalable, optimized, secure RTOS for multiple hardware architectures.
exploring systematic npu codesign
Gemmini extensions for Spike
Configurable low-precision floating-point and microscaling hardware in Chisel
An open-source UCIe implementation
Generating Schedules for Robotic Workloads
Blast your models
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