feat: deterministic row layout for decoupling cap partitions

[Guz007]

Summary

• When partitionType === "decoupling_caps", SingleInnerPartitionPackingSolver now bypasses PackSolver2 and places capacitors in a deterministic centered horizontal row
• Caps sorted by chipId for consistent ordering across runs
• Spacing uses decouplingCapsGap with fallback to chipGap
• Non-decoupling partitions continue through the existing PackSolver2 path unchanged

What changed

lib/solvers/PackInnerPartitionsSolver/SingleInnerPartitionPackingSolver.ts

• Added createDecouplingCapRowLayout() — sorts chips by chipId, computes total row width, centers at origin
• Added early-exit in _step() for partitionType === "decoupling_caps" before PackSolver2 initialization

tests/SingleInnerPartitionPackingSolver/DecouplingCapRow.test.ts (new)

• 3-cap centered row (order, centering, y=0, rotation=0)
• decouplingCapsGap spacing when provided
• chipGap fallback when decouplingCapsGap absent
• Single cap at origin
• Non-decoupling partition regression guard

Verification

bun test tests/SingleInnerPartitionPackingSolver/DecouplingCapRow.test.ts
# 5 pass, 0 fail

bun test
# 27 pass (was 22), 1 fail (pre-existing circuit-to-svg import error in deps), 0 new failures

/claim #15

[vercel]

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