Fix: Implementation of Upward Bias for Voltage Nets #12#79
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…sue tscircuit#12) Introduces preferUpwardRouting flag and applyVoltageBias logic to align VCC/V* nets to the top of the layout, following EE conventions.
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This PR addresses the bad layout issue by implementing a 'Positive Voltage Bias' rule. It ensures that components connected to voltage nets (VCC, 3.3V, etc.) are preferred to route upward. Includes a reproduction script and a new module for voltage bias logic.