double-pulse-test

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KKKevinZhang / Gate-Driver-Circuit-Design-and-PCB-Layout-Optimization-for-SiC-MOSFET

Hardware implementation of a Double Pulse Test (DPT) platform for SiC MOSFETs. Features LTspice parasitic modeling, ANSYS Q3D extraction, and a novel 4-layer Vertical Multi-Loop PCB layout that minimizes parasitic inductance and switching losses for high-frequency wide-bandgap applications.

pcb-layout power-electronics ansys altium-designer ltspice hardware-design sic-mosfet double-pulse-test wide-bandgap-semiconductors

Updated Aug 14, 2026

treiter81 / SiSiC_Fusion_SwitchingEnergyShareRate

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Supporting data for T. Reiter, M. Niendorf, J. Schapdick, "A Method for Individual Switching Energy Extraction in Si/SiC Fusion Switches", ECCE Europe, 2026 (planned publication)

ieee sic igbt sic-mosfet double-pulse-test si-sic-fusion wide-bandgap semiconductor-device-characterization iec60747 switching-energy switching-speed

Updated Mar 15, 2026
MATLAB

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