Intel Quartus Prime Synthesis Engine for Docker

A sample design of Nios with on-board SDRAM for CYC1000 (a low cost Cyclone10 FPGA board)

Game development library for MKR VIDOR 4000

Synchronous Redundant Ring Channel Bus

A simple implementation of outputting ws2812b data using the Cyclone 10 LP evaluation kit.

Hardware implementation of graphics library for MKR VIDOR 4000

VHDL training, ws2812b driver with effect

Uart memory mapped with Avalon-MM interface

VHDL training

Universal Asynchronous Receiver Transmitter

VHDL training, ws2812b driver

ws2812b driver with double buffering and avalon memory mapped interface