[floitsch]

ESP32-S3 I2C targets currently initialize with a zero input-filter threshold. Short line glitches can advance the target state machine and terminate reads early. Set the SDA and SCL input filters to seven cycles, matching the usual master configuration; other targets are unchanged.

Add a single-board slave-v2 regression that checks both filters on both S3 controllers over three open/close cycles, including reopening after a different filter setting. Register the slave-v2 single-board test configuration for ESP32-S3.

Validation:

• Built the full ESP-IDF I2C test application for ESP32-S3 with slave_v2 enabled.
• Ran the new native regression on an ESP32-S3 rev. 0.2 using identical test code: original driver failed (Expected 7 Was 0); patched driver passed (1 Tests 0 Failures 0 Ignored).
• The same driver change previously passed 2,100 concurrent EC618-to-S3 reads across 50/100/400 kHz and 1–513-byte transfers. With external pull-ups verified, a concurrent 100 kHz test passed 500 checked EC618 reads while a classic ESP32 completed 2,000 reads on the other S3 controller.
• Restored the S3's original application from a fresh flash backup and verified all three rig boards responded afterward.

The register regression checks initialization and reuse; it does not inject electrical glitches or establish a precise pulse-rejection limit. The CI configuration is added and builds locally; remote hardware CI has not run yet.