Skip to content
View thierry-gx's full-sized avatar
2 followers · 3 following

Block or report thierry-gx

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories Loading

  1. rv32i-pipelined-cpu rv32i-pipelined-cpu Public

    32-bit, 5-stage pipelined RISC-V CPU (RV32I) implemented in SystemVerilog with full hazard management.l

    SystemVerilog 1

  2. digital-comm-system-sim digital-comm-system-sim Public

    End-to-end simulation of a digital baseband communication system, including sampling, multi-level line coding, AWGN channel, and pulse shaping filters.

    MATLAB 1

  3. rudp-python-implementation rudp-python-implementation Public

    Python implementation of a Reliable User Datagram Protocol (RUDP) over standard UDP sockets, featuring Stop-and-Wait and Go-Back-N (Sliding Window) ARQ mechanisms.

    Python 1