- 🎓 Electrical Engineering @ UET - ⚙️ Into Semiconductors, FPGA, and SystemVerilog (RTL mindset only 😤)
- 🐧 Linux power user (Fedora + Hyprland. I rice, therefore I am)
- 🧪 I break things → then pretend it was part of the design
- 🧠 Designing RTL (Currently grinding on a 5-stage pipelined RISC-V processor)
- 🔌 Playing with FPGA (Nexys A7 gang)
- 🤖 Building embedded projects (ESP32 sensor fusion & Tiva C robotics)
- 📉 Occasionally touching grass (rare interrupt)
if (code_works) {
dont_touch();
} else {
blame_hardware();
}
⚠️ Disclaimer: My code compiles 50% of the time — every time.