docs: update PerCPU chapter for slot and register-cache design

[agicy]

Summary

Rewrite the "PerCPU" chapter (src/chap04/subchap01/PerCPU.md) to describe hvisor's current per-CPU design. The chapter now covers:

• per-CPU slot memory layout (PER_CPU_ARRAY_PTR + cpuid * PER_CPU_SIZE, stack above the slot);
• caching the slot base in a per-arch register (TPIDR_EL2 / IA32_GS_BASE / CSR_SSCRATCH / root CSR SAVE0) with per-arch semantics, behind the uniform set_this_cpu_pointer / this_cpu_pointer accessors;
• the local (this_cpu_data() / this_cpu_id()) vs remote (get_cpu_data()) access interfaces;
• boot-time ordering and the safety invariants that guarantee "register written before any read";
• remote-indexed per-CPU structures (event queues, guest HWI bitmap) stored as MAX_CPU_NUM arrays.

Motivation

The previous version of this chapter predates recent per-CPU implementation changes (register-based slot-pointer caching, new struct fields) and no longer matches the code. The rewrite describes the design as it stands so the book remains an accurate reference for developers reading the source.

Verification

• mdbook build passes with no warnings.
• SUMMARY entry unchanged (same file path).

Risks and Limitations

• Code-driven chapter: field names and layout mirror src/cpu_data.rs and the per-arch cpu.rs; revisit if the per-CPU mechanism changes again.

References

Related: hvisor #392.