Implementation of a 16-bit RISC processor designed for the Computer Organization and Microprocessor (ENCS2380) course at Birzeit University. This project utilizes the Logisim simulator to model and verify a single-cycle datapath and control unit.
- Architecture: 16-bit RISC processor with 16-bit instructions.
- Registers: Includes eight 16-bit registers (R0 to R7).
- Hardwired Zero: R0 is connected to zero; reading it returns 0, and writing to it has no effect.
- Memory: 16-bit addressable memory with separate Instruction and Data segments (Harvard Architecture).
- PC Register: 16-bit register containing the current instruction address.
The processor supports four instruction formats:
| Format | Description | Field Breakdown |
|---|---|---|
| R-type | Register operations | Opcode (5b), rs1 (3b), rs2 (3b), rd (3b), func (2b) |
| I-type | Immediate operations | Opcode (5b), rs1 (3b), rd (3b), Immediate (5b) |
| SB-type | Branch operations | Opcode (5b), rs1 (3b), rs2 (3b), Split Imm (5b) |
| J-type | Jump operations | Opcode (5b), Immediate (11b) |
The 16-bit ALU handles the following sequence of operations:
- Arithmetic: ADD, SUB.
- Logical: AND, OR, XOR.
- Shifts: SLL, SRL, SRA.
- Comparison: SLT (Signed), SLTU (Unsigned).
- Special: Support for LUI (Load Upper Immediate).
- Stack Management: Register R6 is dedicated as the stack pointer, with the stack segment growing backwards in data memory.
- Control Flow: Supports PC-relative addressing for branches and jumps (J, JAL).
- Subroutine Support: JAL and JALR instructions save the return address (PC + 1) in R7 or a specified Rd.
- Memory Access: Displacement addressing is used for Load Word (LW) and Store Word (SW).
- Phase 1: Implementation of the Register File (2 read ports, 1 write port) and the ALU.
- Phase 2: Assembly of the Full Datapath including PC, Instruction Memory, and Data Memory.
- Phase 3: Design of Control Units (Main and PC control) and final system integration.
University: Birzeit University
Course: ENCS2380 - Project #1