sync: rust.beta -> 8ea38001b9da1d6683ac5ebbc993cac89d3a09df

patches/llvm/23.1/0001-MOS-Add-the-llvm-mos-backend.patch

@@ -2037,7 +2037,7 @@ index 6fdd603092fc6b32ab479d444944e013cb5ba274..a804e4d112bbb0cb8e689c9e92bc20ef
 
    /// The integer bit size to use for SjLj based exception handling.
 diff --git a/llvm/include/llvm/TargetParser/Triple.h b/llvm/include/llvm/TargetParser/Triple.h
-index d819c4975b13e5190611b78c8e37cb95e5ebde19..c0b9e8de2c7c71dfc3f8b48fdecea834b46ae3c4 100644
+index c5af232523c695764e369a29ec85e875e9ab1696..816dfa22447af1b43b8df14404170226fb99278c 100644
 --- a/llvm/include/llvm/TargetParser/Triple.h
 +++ b/llvm/include/llvm/TargetParser/Triple.h
 @@ -68,6 +68,7 @@ public:
@@ -2048,7 +2048,7 @@ index d819c4975b13e5190611b78c8e37cb95e5ebde19..c0b9e8de2c7c71dfc3f8b48fdecea834
      msp430,      // MSP430: msp430
      ppc,         // PPC: powerpc
      ppcle,       // PPCLE: powerpc (little endian)
-@@ -1230,6 +1231,11 @@ public:
+@@ -1237,6 +1238,11 @@ public:
      return Env == Triple::GNUX32 || Env == Triple::MuslX32;
    }
 
@@ -30537,10 +30537,10 @@ index bf91c53270067f85681d6119d083aeb60537fcfd..ced5562296ec28582028bc66b27595bc
      MRI = &MF.getRegInfo();
    }
 diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
-index bbd1738cd511719ffe260c23d3e6c938ec6b8d58..e98e31f831af20874d05beb988c767541d4ba35f 100644
+index 8eb20927fb8a088627d48b81ddaf415ffa7da72c..5f682325af35739bf5bb653c16012c83b69c68f6 100644
 --- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
 +++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
-@@ -2629,6 +2629,8 @@ bool RISCVFrameLowering::isSupportedStackID(TargetStackID::Value ID) const {
+@@ -2634,6 +2634,8 @@ bool RISCVFrameLowering::isSupportedStackID(TargetStackID::Value ID) const {
    case TargetStackID::SGPRSpill:
    case TargetStackID::WasmLocal:
    case TargetStackID::ScalablePredicateVector:
@@ -30678,7 +30678,7 @@ index 18f0c13907e52db48fca08f65cf54f1f49b46a20..4457b7f163838cb2489f5d9064ffe86f
      return "e-m:e-p:16:16-i32:16-i64:16-f32:16-f64:16-a:8-n8:16-S16";
    case Triple::ppc:
 diff --git a/llvm/lib/TargetParser/Triple.cpp b/llvm/lib/TargetParser/Triple.cpp
-index 356782c1f6ad49fa75ea774c96865ea401cec0b8..d88fad94c036689766d328060c6eec4449d0ec76 100644
+index 2e4fe7ce70887e38e54239a9f2c6f10bd1873efe..8e1129b1a102cd0f9f5497fe3ab4d011a7b54a4b 100644
 --- a/llvm/lib/TargetParser/Triple.cpp
 +++ b/llvm/lib/TargetParser/Triple.cpp
 @@ -92,6 +92,8 @@ StringRef Triple::getArchTypeName(ArchType Kind) {
@@ -30690,7 +30690,7 @@ index 356782c1f6ad49fa75ea774c96865ea401cec0b8..d88fad94c036689766d328060c6eec44
    case msp430:
      return "msp430";
    case nvptx64:
-@@ -410,6 +412,9 @@ StringRef Triple::getArchTypePrefix(ArchType Kind) {
+@@ -412,6 +414,9 @@ StringRef Triple::getArchTypePrefix(ArchType Kind) {
    case loongarch64:
      return "loongarch";
 
@@ -30700,63 +30700,63 @@ index 356782c1f6ad49fa75ea774c96865ea401cec0b8..d88fad94c036689766d328060c6eec44
    case dxil:
      return "dx";
 
-@@ -565,6 +570,7 @@ Triple::ArchType Triple::getArchTypeForLLVMName(StringRef Name) {
+@@ -567,6 +572,7 @@ Triple::ArchType Triple::getArchTypeForLLVMName(StringRef Name) {
        .Case("csky", csky)
        .Case("loongarch32", loongarch32)
        .Case("loongarch64", loongarch64)
 +      .Case("mos", mos)
        .Case("dxil", dxil)
        .Case("xtensa", xtensa)
        .Default(UnknownArch);
-@@ -663,6 +669,7 @@ Triple::ArchType Triple::parseArch(StringRef ArchName) {
+@@ -666,6 +672,7 @@ Triple::ArchType Triple::parseArch(StringRef ArchName) {
            .Case("thumbeb", Triple::thumbeb)
            .Case("avr", Triple::avr)
            .Case("m68k", Triple::m68k)
 +          .Case("mos", Triple::mos)
            .Case("msp430", Triple::msp430)
            .Cases({"mips", "mipseb", "mipsallegrex", "mipsisa32r6", "mipsr6"},
                   Triple::mips)
-@@ -1021,6 +1028,7 @@ static Triple::ObjectFormatType getDefaultFormat(const Triple &T) {
+@@ -1026,6 +1033,7 @@ static Triple::ObjectFormatType getDefaultFormat(const Triple &T) {
    case Triple::mips64:
    case Triple::mips64el:
    case Triple::mips:
 +  case Triple::mos:
    case Triple::msp430:
    case Triple::nvptx64:
    case Triple::nvptx:
-@@ -1774,6 +1782,7 @@ unsigned Triple::getArchPointerBitWidth(llvm::Triple::ArchType Arch) {
+@@ -1779,6 +1787,7 @@ unsigned Triple::getArchPointerBitWidth(llvm::Triple::ArchType Arch) {
      return 0;
 
    case llvm::Triple::avr:
 +  case llvm::Triple::mos:
    case llvm::Triple::msp430:
      return 16;
 
-@@ -1882,6 +1891,7 @@ Triple Triple::get32BitArchVariant() const {
+@@ -1887,6 +1896,7 @@ Triple Triple::get32BitArchVariant() const {
    case Triple::avr:
    case Triple::bpfeb:
    case Triple::bpfel:
 +  case Triple::mos:
    case Triple::msp430:
    case Triple::systemz:
    case Triple::ve:
-@@ -2000,6 +2010,7 @@ Triple Triple::get64BitArchVariant() const {
+@@ -2005,6 +2015,7 @@ Triple Triple::get64BitArchVariant() const {
    case Triple::kalimba:
    case Triple::lanai:
    case Triple::m68k:
 +  case Triple::mos:
    case Triple::msp430:
    case Triple::r600:
    case Triple::shave:
-@@ -2126,6 +2137,7 @@ Triple Triple::getBigEndianArchVariant() const {
+@@ -2131,6 +2142,7 @@ Triple Triple::getBigEndianArchVariant() const {
    case Triple::kalimba:
    case Triple::loongarch32:
    case Triple::loongarch64:
 +  case Triple::mos:
    case Triple::msp430:
    case Triple::nvptx64:
    case Triple::nvptx:
-@@ -2266,6 +2278,7 @@ bool Triple::isLittleEndian() const {
+@@ -2271,6 +2283,7 @@ bool Triple::isLittleEndian() const {
    case Triple::loongarch64:
    case Triple::mips64el:
    case Triple::mipsel:

patches/rust/1.100/0001-Add-MOS-6502-targets-llvm-mos-backend.patch

@@ -107,7 +107,7 @@ index 6f9751e8074908f0eb329d24d57ab0fb166ca18b..1b0eb7fcd45dc8436ab8dc36c262acd7
      }
  }
 diff --git a/compiler/rustc_target/src/callconv/mod.rs b/compiler/rustc_target/src/callconv/mod.rs
-index edc23b6c50b45b85af98783abac80917cf6c3527..04852d80794c0680f6689e74589750dfd913d332 100644
+index 6be16e8d822aed3a5dd88341c220ce876f2fb69e..1b96cae01081130ada107597496e8d49140d7408 100644
 --- a/compiler/rustc_target/src/callconv/mod.rs
 +++ b/compiler/rustc_target/src/callconv/mod.rs
 @@ -19,6 +19,7 @@
@@ -118,7 +118,7 @@ index edc23b6c50b45b85af98783abac80917cf6c3527..04852d80794c0680f6689e74589750df
  mod mips;
  mod mips64;
  mod msp430;
-@@ -778,6 +779,7 @@ pub fn adjust_for_foreign_abi<C>(&mut self, cx: &C, abi: ExternAbi)
+@@ -780,6 +781,7 @@ pub fn adjust_for_foreign_abi<C>(&mut self, cx: &C, abi: ExternAbi)
              Arch::Avr => avr::compute_abi_info(cx, self),
              Arch::LoongArch32 | Arch::LoongArch64 => loongarch::compute_abi_info(cx, self),
              Arch::M68k => m68k::compute_abi_info(cx, self),

versions.toml

@@ -9,9 +9,9 @@ llvm_commit = "1b9c0d5ff9bbe7634aead059efe6b11a7eeba145"
 [rust.beta]
 # rust-lang/rust has no beta tags: beta is tracked by the `beta` branch head.
 tag = "1.100.0-beta"
-commit = "a2eb6097d22d908142aa4a067bc2cb70860a95b7"
+commit = "8ea38001b9da1d6683ac5ebbc993cac89d3a09df"
 llvm_branch = "rustc/23.1-2026-07-22"
-llvm_commit = "1b9c0d5ff9bbe7634aead059efe6b11a7eeba145"
+llvm_commit = "aab11ee0ea5ea9a1d462ad0bc1fae9d9bb643019"
 
 [llvm_mos]
 base_merge = "cdfebee3c9da537c00e74a650aa8fa5201a97c6f"   # upstream parent ecd2b6862c31