RFC: add testcase for new p extension#648
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- Add rv64up/ and rv32up/ directories for P-extension tests - Add Makefrag files for both directories - Update main Makefile to include P-extension tests - Add padd_b test as initial test case - Use -march=rv64gp and -march=rv32gp for compilation Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Tests for: pli_b, pli_h, plui_h Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Tests for packed add/sub instructions: - padd_bs, padd_h, padd_hs (packed add with saturation) - psub_b, psub_h (packed sub) - paadd_b, paadd_h, paaddu_b, paaddu_h (packed averaging add) - pasub_b, pasub_h, pasubu_b, pasubu_h (packed averaging sub) - psadd_b, psadd_h, psaddu_b, psaddu_h (packed saturating add) - pssub_b, pssub_h, pssubu_b, pssubu_h (packed saturating sub) - psh1add_h, pssh1sadd_h (packed shift-and-add) - aadd, aaddu, asub, asubu (RV32-only averaging) - sadd, saddu, ssub, ssubu, ssh1sadd (RV32-only saturating) Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Tests for: paas_hx, pas_hx, pasa_hx, psa_hx, psas_hx, pssa_hx Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Tests for: pabd_b, pabd_h, pabdu_b, pabdu_h, psabs_b, psabs_h Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Tests for: pabdsumau_b, pabdsumu_b, predsum_bs, predsum_hs, predsumu_bs, predsumu_hs Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Tests for: psati_h, psext_h_b, pusati_h, sati (RV32-only), usati (RV32-only) Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Tests for: psll_bs, psll_hs, pslli_b, pslli_h, psra_bs, psra_hs, psrai_b, psrai_h, psrari_h, psrl_bs, psrl_hs, psrli_b, psrli_h, pssha_hs, psshar_hs, psslai_h, srari (RV32-only), ssha (RV32-only), sshar (RV32-only), sslai (RV32-only) Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Tests for: pmax_b, pmax_h, pmaxu_b, pmaxu_h, pmin_b, pmin_h, pminu_b, pminu_h, pmseq_b, pmseq_h, pmslt_b, pmslt_h, pmsltu_b, pmsltu_h, mseq (RV32-only), mslt (RV32-only), msltu (RV32-only) Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Tests for: pack, ppaire_b, ppaireo_b, ppaireo_h, ppairo_b, ppairo_h, ppairoe_b, ppairoe_h Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Tests for: abs, cls, merge, mvm, mvmn, slx, srx (all RV32-only) Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Tests for: pmul_h_b00, pmul_h_b01, pmul_h_b11, pmulh_h_b0, pmulh_h_b1, pmulh_h, pmulhr_h, pmulhrsu_h, pmulhru_h, pmulhsu_h_b0, pmulhsu_h_b1, pmulhsu_h, pmulhu_h, pmulq_h, pmulqr_h, pmulsu_h_b00, pmulsu_h_b11, pmulu_h_b00, pmulu_h_b01, pmulu_h_b11 RV32-only: mul_h00, mul_h01, mul_h11, mulh_h0, mulh_h1, mulhr, mulhrsu, mulhru, mulhsu_h0, mulhsu_h1, mulq, mulqr, mulsu_h00, mulsu_h11, mulu_h00, mulu_h01, mulu_h11 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Tests for: pmhacc_h, pmhacc_h_b0, pmhacc_h_b1, pmhaccsu_h, pmhaccsu_h_b0, pmhaccsu_h_b1, pmhaccu_h, pmhracc_h, pmhraccsu_h, pmhraccu_h RV32-only: macc_h00, macc_h01, macc_h11, maccsu_h00, maccsu_h11, maccu_h00, maccu_h01, maccu_h11, mhacc, mhacc_h0, mhacc_h1, mhaccsu, mhaccsu_h0, mhaccsu_h1, mhaccu, mhracc, mhraccsu, mhraccu, mqacc_h00, mqacc_h01, mqacc_h11, mqracc_h00, mqracc_h01, mqracc_h11 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Tests for: pm2add_h, pm2add_hx, pm2adda_h, pm2adda_hx, pm2addasu_h, pm2addau_h, pm2addsu_h, pm2addu_h, pm2sadd_h, pm2sadd_hx, pm2sub_h, pm2sub_hx, pm2suba_h, pm2suba_hx, pm4add_b, pm4adda_b, pm4addasu_b, pm4addau_b, pm4addsu_b, pm4addu_b, pmq2add_h, pmq2adda_h, pmqr2add_h, pmqr2adda_h Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Tests for: psati_w, psext_w_b, psext_w_h, pusati_w (all RV64-only) Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Tests for: absw, clsw (all RV64-only) Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Tests for: pli_db, pli_dh, plui_dh (all RV32-only, register-pair) Added to Makefrag. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Tests for: addd, subd, padd_db, padd_dbs, padd_dh, padd_dhs, padd_dw, padd_dws, psub_db, psub_dh, psub_dw, paadd_db, paadd_dh, paadd_dw, paaddu_db, paaddu_dh, paaddu_dw, pasub_db, pasub_dh, pasub_dw, pasubu_db, pasubu_dh, pasubu_dw, psadd_db, psadd_dh, psadd_dw, psaddu_db, psaddu_dh, psaddu_dw, pssub_db, pssub_dh, pssub_dw, pssubu_db, pssubu_dh, pssubu_dw, psh1add_dh, psh1add_dw, pssh1sadd_dh, pssh1sadd_dw, pwadd_b, pwadd_h, pwaddu_b, pwaddu_h, pwadda_b, pwadda_h, pwaddau_b, pwaddau_h, pwsub_b, pwsub_h, pwsubu_b, pwsubu_h, pwsuba_b, pwsuba_h, pwsubau_b, pwsubau_h, wadd, waddu, wadda, waddau, wsub, wsubu, wsuba, wsubau (all RV32-only, register-pair) Added to Makefrag. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Tests for: paas_dhx, pas_dhx, pasa_dhx, psa_dhx, psas_dhx, pssa_dhx (all RV32-only, register-pair) Added to Makefrag. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Tests for: predsum_dbs, predsum_dhs, predsumu_dbs, predsumu_dhs, pabd_db, pabd_dh, pabdu_db, pabdu_dh, psabs_db, psabs_dh (all RV32-only, register-pair) Note: rd and rs1 must be even registers (register-pair constraint). For psabs instructions, the format is unary: rd, rs1 (no rs2). Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Tests for: psext_dh_b, psext_dw_b, psext_dw_h (all RV32-only, register-pair) Note: rd and rs1 must be even registers (register-pair constraint). These are unary operations: rd, rs1 (no rs2). Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Tests for: pwsla_bs, pwsla_hs, pwslai_b, pwslai_h, pwsll_bs, pwsll_hs, pwslli_b, pwslli_h, wsla, wsll (all RV32-only, register-pair) Added to Makefrag. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Tests for: pwmul_b, pwmul_h, pwmulsu_b, pwmulsu_h, pwmulu_b, pwmulu_h, wmul, wmulsu, wmulu (all RV32-only, register-pair) Added to Makefrag. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Tests for: pwmacc_h, pwmaccsu_h, pwmaccu_h, wmacc, wmaccsu, wmaccu (all RV32-only, register-pair) Added to Makefrag. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Tests for: mqwacc, pmqwacc_h, mqrwacc, pmqrwacc_h (all RV32-only, register-pair) Added to Makefrag. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Tests for: psll_dbs, psll_dhs, psll_dws, pslli_db, pslli_dh, pslli_dw, psra_dbs, psra_dhs, psra_dws, psrl_dbs, psrl_dhs, psrl_dws, pssha_dhs, pssha_dws, psshar_dhs, psshar_dws, psslai_dh, psslai_dw, wslai, wslli (all RV32-only, register-pair) Note: rd and rs1 must be even registers (register-pair constraint). Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Tests for: pmax_db, pmax_dh, pmax_dw, pmaxu_db, pmaxu_dh, pmaxu_dw, pmin_db, pmin_dh, pmin_dw, pminu_db, pminu_dh, pminu_dw, pmseq_db, pmseq_dh, pmseq_dw, pmslt_db, pmslt_dh, pmslt_dw, pmsltu_db, pmsltu_dh, pmsltu_dw (all RV32-only, register-pair) Note: rd and rs1 must be even registers (register-pair constraint). Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Tests for: ppaire_db, ppaire_dh, ppaireo_db, ppaireo_dh, ppairo_db, ppairo_dh, ppairoe_db, ppairoe_dh (all RV32-only, register-pair) Note: rd and rs1 must be even registers (register-pair constraint). Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Tests for: psati_dh, psati_dw, pusati_dh, pusati_dw (all RV32-only, register-pair) Added to Makefrag. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Tests for: psrai_db, psrai_dh, psrai_dw, psrari_dh, psrari_dw, psrli_db, psrli_dh, psrli_dw (all RV32-only, register-pair) Added to Makefrag. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Tests for: - 1b: mul_w00, mul_w01, mul_w11, mulu_w00, mulu_w01, mulu_w11, mulsu_w00, mulsu_w11 (8 instructions) - 1c: macc_w00, macc_w01, macc_w11, maccu_w00, maccu_w01, maccu_w11, maccsu_w00, maccsu_w11 (8 instructions) - 1d: mqacc_w00, mqacc_w01, mqacc_w11, mqracc_w00, mqracc_w01, mqracc_w11 (6 instructions) All RV64-only instructions for 32-bit word multiply and multiply-accumulate operations. Instruction format: rd, rs1, rs2 - _w00: low word * low word - _w01: low word * high word - _w11: high word * high word - u suffix: unsigned - su suffix: signed * unsigned - mq/mqr: Q31 format (with/without rounding) Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Tests for: - paadd_w, paaddu_w, pasub_w, pasubu_w (4 instructions) - padd_w, padd_ws (2 instructions) - paas_wx, pas_wx, pasa_wx, psa_wx, psas_wx, pssa_wx (6 instructions) - pli_w, plui_w (2 instructions) - psub_w (1 instruction) All RV64-only packed word instructions for: - Averaging add/sub (signed/unsigned) - Add with scalar broadcast - Cross add-sub (averaging, plain, saturating) - Load immediate to all word elements - Packed word subtraction Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Tests for: - pm2add_w, pm2add_wx, pm2addu_w, pm2addsu_w, pm2adda_w, pm2adda_wx, pm2addau_w, pm2addasu_w (8 instructions) - pm2sub_w, pm2sub_wx, pm2suba_w, pm2suba_wx (4 instructions) - pm4add_h, pm4adda_h, pm4addu_h, pm4addau_h, pm4addsu_h, pm4addasu_h (6 instructions) These are RV64-only packed multiply reduction instructions: - pm2add/sub_w: 2-way multiply add/sub for 32-bit words -> 64-bit result - pm4add_h: 4-way multiply add for 16-bit halfwords -> 64-bit result Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Tests for: - pmacc_w_h00, pmacc_w_h01, pmacc_w_h11, pmaccu_w_h00, pmaccu_w_h01, pmaccu_w_h11, pmaccsu_w_h00, pmaccsu_w_h11 (8 instructions) - pmhacc_w, pmhacc_w_h0, pmhacc_w_h1, pmhaccu_w, pmhaccsu_w, pmhaccsu_w_h0, pmhaccsu_w_h1, pmhracc_w, pmhraccu_w, pmhraccsu_w (10 instructions) - pmqacc_w_h00, pmqacc_w_h01, pmqacc_w_h11, pmqracc_w_h00, pmqracc_w_h01, pmqracc_w_h11 (6 instructions) These are RV64-only packed multiply-accumulate instructions for 32-bit words: - pmacc_w: multiply-accumulate using halfword selections - pmhacc_w: multiply-high accumulate - pmqacc_w: Q-format multiply accumulate Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Tests for: - pmax_w, pmaxu_w, pmin_w, pminu_w, pmseq_w, pmslt_w, pmsltu_w (7 instructions) These are RV64-only packed comparison instructions for 32-bit words: - pmax/pmin: packed max/min (signed and unsigned) - pmseq: packed mask set equal - pmslt/pmsltu: packed mask set less than (signed and unsigned) Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Tests for: - pmq2add_w, pmq2adda_w, pmqr2add_w, pmqr2adda_w (4 instructions) These are RV64-only packed multiply Q31 2-way add instructions for 32-bit words: - pmq2add_w: Q31 multiply 2-way add - pmq2adda_w: Q31 multiply 2-way add accumulate - pmqr2add_w: Q31 multiply rounding 2-way add - pmqr2adda_w: Q31 multiply rounding 2-way add accumulate Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Tests for: - pmul_w_h00, pmul_w_h01, pmul_w_h11, pmulh_w, pmulh_w_h0, pmulh_w_h1, pmulhr_w, pmulhru_w, pmulhrsu_w, pmulhsu_w, pmulhsu_w_h0, pmulhsu_w_h1, pmulhu_w, pmulq_w, pmulqr_w, pmulsu_w_h00, pmulsu_w_h11, pmulu_w_h00, pmulu_w_h01, pmulu_w_h11 (20 instructions) These are RV64-only packed multiply instructions for 32-bit words: - pmul_w: 16-bit to 32-bit widening multiply (signed) - pmulh_w: multiply high (signed) - pmulhr_w: multiply high rounding (signed) - pmulhru_w: multiply high rounding (unsigned) - pmulhrsu_w: multiply high rounding (signed*unsigned) - pmulhsu_w: multiply high (signed*unsigned) - pmulhu_w: multiply high (unsigned) - pmulq_w: Q31 multiply - pmulqr_w: Q31 multiply rounding - pmulsu_w: 16-bit to 32-bit widening multiply (signed*unsigned) - pmulu_w: 16-bit to 32-bit widening multiply (unsigned) Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Tests for: - ppaire_h, ppaireo_w, ppairoe_w, ppairo_w (4 instructions) - predsum_ws, predsumu_ws (2 instructions) These are RV64-only packed instructions for: - Pair selection (even/odd word combinations) - Reduction sum for 32-bit words (signed and unsigned) Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Tests for: - psadd_w, psaddu_w, pssub_w, pssubu_w (4 instructions) These are RV64-only packed saturating arithmetic instructions for 32-bit words: - psadd_w: saturating add (signed) - psaddu_w: saturating add (unsigned) - pssub_w: saturating subtract (signed) - pssubu_w: saturating subtract (unsigned) Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Tests for: - psll_ws, pslli_w, psra_ws, psrai_w, psrari_w, psrl_ws, psrli_w, pssha_ws, psshar_ws, psslai_w (10 instructions) These are RV64-only packed shift instructions for 32-bit words: - psll_ws/pslli_w: shift left logical (scalar/immediate) - psra_ws/psrai_w: shift right arithmetic (scalar/immediate) - psrari_w: shift right arithmetic rounding immediate - psrl_ws/psrli_w: shift right logical (scalar/immediate) - pssha_ws: saturating shift arithmetic (bidirectional) - psshar_ws: saturating shift arithmetic rounding (bidirectional) - psslai_w: saturating shift left arithmetic immediate Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Tests for: - psh1add_w, pssh1sadd_w (2 instructions) These are RV64-only packed shift-1-and-add instructions for 32-bit words: - psh1add_w: shift left by 1 and add - pssh1sadd_w: saturating shift left by 1 and saturating add Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Tests for: - sha, shar (2 instructions) These are RV64-only scalar bidirectional shift instructions: - sha: bidirectional arithmetic shift (positive = left, negative = right) - shar: bidirectional arithmetic shift with rounding on right shift Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Tests for: - pnsra_bs, pnsra_hs, pnsrai_b, pnsrai_h, pnsrar_bs, pnsrar_hs, pnsrari_b, pnsrari_h, pnsrl_bs, pnsrl_hs, pnsrli_b, pnsrli_h (12 instructions) These are RV32-only narrowing shift instructions that: - Use register pairs (rs1, rs1+1) as 64-bit input - Narrow to 32-bit output in rd - Include logical, arithmetic, and rounding variants Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Tests for: - pnclip_bs, pnclip_hs, pnclipi_b, pnclipi_h, pnclipiu_b, pnclipiu_h, pnclipr_bs, pnclipr_hs, pnclipri_b, pnclipri_h, pnclipriu_b, pnclipriu_h, pnclipru_bs, pnclipru_hs, pnclipu_bs, pnclipu_hs (16 instructions) These are RV32-only narrowing clip instructions that: - Use register pairs (rs1, rs1+1) as 64-bit input - Shift right, optionally round, then saturate to smaller element size - Include signed (clip) and unsigned (clipu) variants - Include rounding (r) variants Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Tests for: - pm2wadd_h, pm2wadd_hx, pm2wadda_h, pm2wadda_hx, pm2waddu_h, pm2waddsu_h, pm2waddau_h, pm2waddasu_h (8 instructions) - pm2wsub_h, pm2wsub_hx, pm2wsuba_h, pm2wsuba_hx (4 instructions) These are RV32-only widening 2-way multiply instructions that: - Take packed 16-bit halfword elements as input - Produce 64-bit widening results in register pair (rd, rd+1) - Include signed, unsigned, and signed-unsigned variants - Include accumulate variants that add to rd_pair Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Add 7 new tests for RV32-only scalar narrow instructions: - nsrai: narrow shift right arithmetic immediate - nsrli: narrow shift right logical immediate - nsrari: narrow shift right arithmetic rounding immediate - nclipi: narrow clip immediate (signed) - nclipiu: narrow clip immediate unsigned - nclipri: narrow clip rounding immediate (signed) - nclipriu: narrow clip rounding immediate unsigned These instructions take 64-bit input from register pair (rs1, rs1+1) and output 32-bit result to rd. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Add 4 new tests for RV32-only scalar narrow clip instructions: - nclip: narrow clip (signed, register shift) - nclipu: narrow clip unsigned (register shift) - nclipr: narrow clip rounding (signed, register shift) - nclipru: narrow clip rounding unsigned (register shift) These instructions take 64-bit input from register pair (rs1, rs1+1), shift by rs2, saturate, and output 32-bit result to rd. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Add 3 new tests for RV32-only scalar narrow shift instructions: - nsra: narrow shift right arithmetic (register shift) - nsrl: narrow shift right logical (register shift) - nsrar: narrow shift right arithmetic rounding (register shift) These instructions take 64-bit input from register pair (rs1, rs1+1), shift by rs2, and output 32-bit result to rd. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Add 3 new tests for RV64-only instructions: - sati: saturate signed - usati: saturate unsigned - srari: shift right arithmetic rounding immediate Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Add 8 new tests for RV64 zip/unzip instructions: - zip8p: zip 8-bit elements - zip16p: zip 16-bit elements - zip8hp: zip 8-bit elements (high part) - zip16hp: zip 16-bit elements (high part) - unzip8p: unzip 8-bit elements - unzip16p: unzip 16-bit elements - unzip8hp: unzip 8-bit elements (high part) - unzip16hp: unzip 16-bit elements (high part) Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Add 2 new tests for RV32-only widening zip instructions: - wzip8p: widening zip 8-bit elements into 16-bit - wzip16p: widening zip 16-bit elements into 32-bit Output is 64-bit in register pair (rd, rd+1). Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Added tests: - rv32up/rev.S: RV32 bit reverse (grevi shamt=31) - rv64up/rev.S: RV64 bit reverse (grevi shamt=63) - rv64up/rev16.S: RV64 16-bit group swap (grevi shamt=48) - rv64up/mvm.S: RV64 move if mask - rv64up/mvmn.S: RV64 move if not mask - rv64up/merge.S: RV64 bitwise merge - rv64up/slx.S: RV64 funnel shift left - rv64up/srx.S: RV64 funnel shift right Updated Makefrags to include new tests. All tests verified passing with spike-cosim. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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The current version is not fully verified with spike implementation because there are some issues in toolchains I can get.