[executorch][cuda] Optimize short-query INT5 matvec kernels - #21458
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[executorch][cuda] Optimize short-query INT5 matvec kernels#21458Gasoonjia wants to merge 1 commit into
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🔗 Helpful Links🧪 See artifacts and rendered test results at hud.pytorch.org/pr/pytorch/executorch/21458
Note: Links to docs will display an error until the docs builds have been completed. ❌ 2 New Failures, 2 Unclassified FailuresAs of commit 0d04c58 with merge base e47f373 ( NEW FAILURES - The following jobs have failed:
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Stack from ghstack (oldest at bottom):
Add specialized M=1 and M=4 short-query paths for the planar INT5 W5A8 matvec operator. These are the latency-sensitive single-row and four-row shapes. M=2/M=3 retain the generic fallback path; this change does not claim those shapes as optimized.
The M=1 implementation shares safe gs32 decode/accumulate logic through a compile-time ROWS device template. M=4 remains explicit because KernelAgent experiments with the generalized template increased register pressure and regressed latency. The final kernels were generated and tuned with KernelAgent.
A100 kernel microbenchmarks versus the previous generic path:
Correctness tests cover M=1,2,3,4 with three randomized seeds; ptxas reports zero spills.
Differential Revision: D114032323