Add Geehy G32R5xx target support.

[quincy-gh]

Summary

• Add builtin targets for Geehy G32R501 (g32r501xx and dual-core g32r501dxx) and G32R502 (g32r502xx).
• The target modules are taken from the Geehy G32R5xx SDK (AN1126). They include the flash algorithm and the DCS key / boot-mode sequences that must run before user flash is visible after reset.
• ITCM and DTCM are marked is_cacheable=False so the debugger memory cache does not cover tightly coupled RAM.

Test plan

• pyocd list --targets lists g32r501xx, g32r501dxx, and g32r502xx (vendor Geehy, source builtin).
• G32R502 on Geehy-Link (Cortex-M52): chip erase, program an ELF, readback match, valid flash vector after DCS, core running in flash with IPSR=0 and CFSR/HFSR clear.
• G32R501 on Geehy CMSIS-DAP (Cortex-M52): chip erase, program an ELF, readback match. After SYSRESETREQ and startup configuration, CPU0 runs in arch_cpu_idle with IPSR=0.
• G32R501 dual-core: a blank CPU1 vector at 0x08050000 leaves the boot-control release bit clear (CPU1 flash vector blank; keeping CPU1 halted).
• CI