Gdbserver update

docs/options.md

@@ -632,6 +632,15 @@ applies while the target is running after a resume operation in the debugger and
 it to halt again.
 </td></tr>
 
+<tr><td>live.status_fault_retry_timeout</td>
+<td>float</td>
+<td>No default</td>
+<td>
+Timeout in seconds for retrying target status reads that fail with a transfer error while a server
+monitors a core. A successful read clears the retry period. If the timeout expires, the server
+instance for that core exits. If the option is omitted, retries continue indefinitely.
+</td></tr>
+
 <tr><td>gdbserver_port</td>
 <td>int</td>
 <td>3333</td>

pyocd/core/options.py

@@ -165,6 +165,10 @@ class OptionInfo(NamedTuple):
         "Duration in seconds that a failed target status check will be retried before an error is raised. "
         "Only applies while the target is running after a resume operation in the debugger and pyOCD is waiting "
         "for it to halt again."),
+    OptionInfo('live.status_fault_retry_timeout', float, None,
+        "Timeout in seconds for retrying target status reads that fail with a transfer error while a server "
+        "monitors a core. A successful read clears the retry period. If the timeout expires, the server "
+        "instance for that core exits. If the option is omitted, retries continue indefinitely."),
     OptionInfo('gdbserver_port', (int, tuple), 3333,
         "Base TCP port for the gdbserver."),
     OptionInfo('persist', bool, False,

pyocd/core/soc_target.py

@@ -264,6 +264,9 @@ def write_core_registers_raw(self, reg_list: Sequence[CoreRegisterNameOrNumberTy
     def find_breakpoint(self, addr: int) -> Optional[Breakpoint]:
         return self.selected_core_or_raise.find_breakpoint(addr)
 
+    def skip_breakpoint_instruction(self, exclude_semihosting: bool = False) -> bool:
+        return self.selected_core_or_raise.skip_breakpoint_instruction(exclude_semihosting)
+
     def set_breakpoint(self, addr: int, type: Target.BreakpointType = Target.BreakpointType.AUTO) -> bool:
         return self.selected_core_or_raise.set_breakpoint(addr, type)
 

pyocd/core/target.py

@@ -273,6 +273,9 @@ def write_core_registers_raw(self, reg_list: Sequence[CoreRegisterNameOrNumberTy
     def find_breakpoint(self, addr: int) -> Optional[Breakpoint]:
         raise NotImplementedError()
 
+    def skip_breakpoint_instruction(self, exclude_semihosting: bool = False) -> bool:
+        raise NotImplementedError()
+
     def set_breakpoint(self, addr: int, type: BreakpointType = BreakpointType.AUTO) -> bool:
         raise NotImplementedError()
 

pyocd/coresight/cortex_m.py

@@ -1206,6 +1206,27 @@ def resume(self) -> None:
     def find_breakpoint(self, addr: int) -> Optional[Breakpoint]:
         return self.bp_manager.find_breakpoint(addr)
 
+    def skip_breakpoint_instruction(self, exclude_semihosting: bool = False) -> bool:
+        """@brief Skip an BKPT instruction.
+
+        @return True if a BKPT instruction was skipped, otherwise False.
+        """
+
+        pc = self.read_core_register('pc')
+
+        instruction = self.read16(pc)
+        if (instruction & 0xff00) != 0xbe00:
+            return False
+
+        if exclude_semihosting and instruction == 0xbeab:
+            return False
+
+        self.write_core_register('pc', pc + 2)
+        LOG.debug("Skipped breakpoint at 0x%08x", pc)
+        self._run_token += 1
+
+        return True
+
     def check_reg_list(self, reg_list: Sequence[CoreRegisterNameOrNumberType]) -> None:
         """@brief Sanity check register values and raise helpful errors."""
         for reg in reg_list:
@@ -1621,16 +1642,16 @@ def get_halt_reason(self) -> Optional[Target.HaltReason]:
         @return @ref pyocd.core.target.Target.HaltReason "Target.HaltReason" enumerator or None.
         """
         dfsr = self.read32(CortexM.DFSR)
-        if dfsr & CortexM.DFSR_HALTED:
-            reason = Target.HaltReason.DEBUG
-        elif dfsr & CortexM.DFSR_BKPT:
+        if dfsr & CortexM.DFSR_BKPT:
             reason = Target.HaltReason.BREAKPOINT
         elif dfsr & CortexM.DFSR_DWTTRAP:
             reason = Target.HaltReason.WATCHPOINT
         elif dfsr & CortexM.DFSR_VCATCH:
             reason = Target.HaltReason.VECTOR_CATCH
         elif dfsr & CortexM.DFSR_EXTERNAL:
             reason = Target.HaltReason.EXTERNAL
+        elif dfsr & CortexM.DFSR_HALTED:
+            reason = Target.HaltReason.DEBUG
         else:
             reason = None
         return reason

pyocd/coresight/cortex_m_v8m.py

@@ -264,9 +264,7 @@ def get_halt_reason(self):
         @return @ref pyocd.core.target.Target.HaltReason "Target.HaltReason" enumerator or None.
         """
         dfsr = self.read32(self.DFSR)
-        if dfsr & self.DFSR_HALTED:
-            reason = Target.HaltReason.DEBUG
-        elif dfsr & self.DFSR_BKPT:
+        if dfsr & self.DFSR_BKPT:
             reason = Target.HaltReason.BREAKPOINT
         elif dfsr & self.DFSR_DWTTRAP:
             reason = Target.HaltReason.WATCHPOINT
@@ -276,6 +274,8 @@ def get_halt_reason(self):
             reason = Target.HaltReason.EXTERNAL
         elif dfsr & self.DFSR_PMU:
             reason = Target.HaltReason.PMU
+        elif dfsr & self.DFSR_HALTED:
+            reason = Target.HaltReason.DEBUG
         else:
             reason = None
         return reason

pyocd/coresight/generic_mem_ap.py

@@ -115,6 +115,9 @@ def resume(self):
     def find_breakpoint(self, addr):
         return None
 
+    def skip_breakpoint_instruction(self, exclude_semihosting: bool = False) -> bool:
+        return False
+
     def read_core_register(self, reg):
         raise exceptions.CoreRegisterAccessError("GenericMemAPTarget does not support core register access")