Do not include unknown files for some script formats

src/cmd/script.rs

@@ -14,6 +14,7 @@ use tokio::runtime::Runtime;
 
 use crate::cmd::sources::get_passed_targets;
 use crate::config::{Validate, ValidationContext};
+use crate::diagnostic::Warnings;
 use crate::error::*;
 use crate::sess::{Session, SessionIo};
 use crate::src::{SourceFile, SourceGroup, SourceType};
@@ -455,6 +456,7 @@ fn emit_template(
     let mut all_files = IndexSet::new();
     let mut all_verilog = vec![];
     let mut all_vhdl = vec![];
+    let mut unknown_files = vec![];
     for src in &srcs {
         all_defines.extend(
             src.defines
@@ -557,7 +559,9 @@ fn emit_template(
             "vhdl" => {
                 all_vhdl.append(&mut src.files.clone().into_iter().collect());
             }
-            _ => {}
+            _ => {
+                unknown_files.append(&mut src.files.clone().into_iter().collect());
+            }
         }
     }
     let split_srcs = if emit_sources { split_srcs } else { vec![] };
@@ -575,6 +579,9 @@ fn emit_template(
     };
     tera_context.insert("all_verilog", &all_verilog);
     tera_context.insert("all_vhdl", &all_vhdl);
+    if !unknown_files.is_empty() && template.contains("file_type") {
+        Warnings::UnknownFileType(unknown_files).emit();
+    }
 
     tera_context.insert("source_annotations", &!args.no_source_annotations);
     tera_context.insert("compilation_mode", &args.compilation_mode);

src/diagnostic.rs

@@ -361,6 +361,15 @@ pub enum Warnings {
     )]
     LfsDisabled(String),
 
+    #[error("{} with unknown type:\n{}", if .0.len() == 1 { "File" } else { "Files" }, .0.iter().map(|p| format!("  - {}", fmt_path!(p.display()))).collect::<Vec<_>>().join("\n"))]
+    #[diagnostic(
+        code(W28),
+        help(
+            "Known file extensions are: .sv, .v, .vp (Verilog) and .vhd, .vhdl (VHDL).\nTo indicate a file type for unknown file extensions, use `sv:`, `v:`, or `vhd:` when listing the file."
+        )
+    )]
+    UnknownFileType(Vec<PathBuf>),
+
     #[error("File not added, ignoring: {cause}")]
     #[diagnostic(code(W30))]
     IgnoredPath { cause: String },

src/script_fmt/formality_tcl.tera

@@ -1,7 +1,7 @@
 # {{HEADER_AUTOGEN}}
 set ROOT "{{ root }}"
 set search_path_initial $search_path
-{% if compilation_mode == 'separate' %}{% for group in srcs %}{% if source_annotations %}
+{% if compilation_mode == 'separate' %}{% for group in srcs %}{% if group.file_type != '' %}{% if source_annotations %}
 # {{ group.metadata }}{% endif %}
 set search_path $search_path_initial
 {% for incdir in group.incdirs %}lappend search_path "$ROOT{{ incdir | replace(from=root, to='') }}"
@@ -15,7 +15,7 @@ set search_path $search_path_initial
     {% for file in group.files %}{{ '    ' }}"{{ file | replace(from=root, to='$ROOT') }}" \
     {% endfor %}]
 {% if abort_on_error %}}]} {return 1}{% endif %}
-{% endfor %}
+{% endif %}{% endfor %}
 {% else %}{# compilation_mode == 'common' #}{% for file in all_verilog %}{% if loop.first %}set search_path $search_path_initial
 {% for incdir in all_incdirs %}lappend search_path "$ROOT{{ incdir | replace(from=root, to='') }}"
 {% endfor %}

src/script_fmt/genus_tcl.tera

@@ -5,7 +5,7 @@ if [ info exists search_path ] {
     set search_path_initial {}
 }
 set ROOT "{{ root }}"
-{% if compilation_mode == 'separate' %}{% for group in srcs %}{% if source_annotations %}
+{% if compilation_mode == 'separate' %}{% for group in srcs %}{% if group.file_type != '' %}{% if source_annotations %}
 # {{ group.metadata }}{% endif %}
 set search_path $search_path_initial
 {% for incdir in group.incdirs %}lappend search_path "{{ incdir | replace(from=root, to='$ROOT') }}"
@@ -20,7 +20,7 @@ set search_path $search_path_initial
         {% endif %}{% endfor %}[list \
     {% for file in group.files %}{{ '    ' }}"{{ file | replace(from=root, to='$ROOT') }}" \
     {% endfor %}]
-{% endfor %}
+{% endif %}{% endfor %}
 {% else %}{# compilation_mode == 'common' #}{% for file in all_verilog %}{% if loop.first %}set search_path $search_path_initial
 {% for incdir in all_incdirs %}lappend search_path "$ROOT{{ incdir | replace(from=root, to='') }}"
 {% endfor %}

src/script_fmt/precision_tcl.tera

@@ -10,7 +10,7 @@ setup_design -defines { \
     {% endif %}+define+{{ define.0 }}{% if define.1 %}={{ define.1 }}{% endif %}{% if loop.last %}
 
 {% else %} \
-    {% endif %}{% endfor %}{% if compilation_mode == 'separate' %}{% for group in srcs %}{% if source_annotations %}# {{ group.metadata }}
+    {% endif %}{% endfor %}{% if compilation_mode == 'separate' %}{% for group in srcs %}{% if group.file_type != '' %}{% if source_annotations %}# {{ group.metadata }}
 {% endif %}{% if abort_on_error %}if {[catch { {% endif %}add_input_file \
     {% if group.file_type == 'verilog' %}-format SystemVerilog2012 \
     {% for incdir in group.incdirs %}{% if loop.first %}-search_path { \
@@ -24,7 +24,7 @@ setup_design -defines { \
         {% endif %}{% endfor %}} \
 {% if abort_on_error %}}]} {return 1}
 {% endif %}
-{% endfor %}
+{% endif %}{% endfor %}
 {% else %}{# compilation_mode == 'common' #}{% for file in all_verilog %}{% if loop.first %}{% if abort_on_error %}if {[catch { {% endif %}add_input_file \
     -format SystemVerilog2012 \
     {% for incdir in all_incdirs %}{% if loop.first %}-search_path { \

src/script_fmt/riviera_tcl.tera

@@ -1,7 +1,7 @@
 # {{ HEADER_AUTOGEN }}
 set ROOT "{{ root }}"
 vlib work
-{% if compilation_mode == 'separate' %}{% for group in srcs %}{% if source_annotations %}# {{ group.metadata }}
+{% if compilation_mode == 'separate' %}{% for group in srcs %}{% if group.file_type != '' %}{% if source_annotations %}# {{ group.metadata }}
 {% endif %}{% if abort_on_error %}if {[catch { {% endif %}{% if group.file_type == 'verilog' %}vlog -sv \
     {% for tmp_arg in vlog_args %}{{ tmp_arg }} \
     {% endfor %}{% for define in group.defines %}"+define+{{ define.0 }}{% if define.1 %}={{ define.1 }}{% endif %}" \
@@ -12,7 +12,7 @@ vlib work
     {% else %}\
 {% endif %}{% endfor %}{% if abort_on_error %}}]} {return 1}{% endif %}
 
-{% endfor %}{% else %}{# compilation_mode == 'common' #}{% for file in all_verilog %}{% if loop.first %}{% if abort_on_error %}if {[catch { {% endif %}vlog -sv \
+{% endif %}{% endfor %}{% else %}{# compilation_mode == 'common' #}{% for file in all_verilog %}{% if loop.first %}{% if abort_on_error %}if {[catch { {% endif %}vlog -sv \
     {% for tmp_arg in vlog_args %}{{ tmp_arg }} \
     {% endfor %}{% for define in all_defines %}"+define+{{ define.0 }}{% if define.1 %}={{ define.1 }}{% endif %}" \
     {% endfor %}{% for incdir in all_incdirs %}"+incdir+{{ incdir | replace(from=root, to='$ROOT') }}" \

src/script_fmt/synopsys_tcl.tera

@@ -2,7 +2,7 @@
 set ROOT "{{ root }}"
 set search_path_initial $search_path
 {% if compilation_mode == 'separate' %}{#                                                                           Individual block for each source file group
-#}{% for group in srcs %}{% if source_annotations %}
+#}{% for group in srcs %}{% if group.file_type != '' %}{% if source_annotations %}
 # {{ group.metadata }}{% endif %}
 set search_path $search_path_initial
 {% for incdir in group.incdirs %}{#                                                                                 Add group's include directories
@@ -27,7 +27,7 @@ set search_path $search_path_initial
 #}{{ '    ' }}"{{ file | replace(from=root, to='$ROOT') }}" \
     {% endfor %}]
 {% if abort_on_error %}]} {return 1}{% endif %}
-{% endfor %}
+{% endif %}{% endfor %}
 {% else %}{# compilation_mode == 'common' #}{#                                                                      Common block for all files
 #}{% for file in all_verilog %}{#                                                                                   Loop over verilog files
 #}{% if loop.first %}set search_path $search_path_initial

src/script_fmt/vcs_sh.tera

@@ -4,7 +4,7 @@
 set -e
 {% endif %}
 ROOT="{{ root }}"
-{% if compilation_mode == 'separate' %}{% for group in srcs %}{% if source_annotations %}
+{% if compilation_mode == 'separate' %}{% for group in srcs %}{% if group.file_type != '' %}{% if source_annotations %}
 # {{ group.metadata }}{% endif %}
 {% if group.file_type == 'verilog' %}{{ vlogan_bin }} -sverilog \
     -full64 \
@@ -15,7 +15,7 @@ ROOT="{{ root }}"
     {% for tmp_arg in vhdlan_args %}{{ tmp_arg }} \
     {% endfor %}{% endif %}{% for file in group.files %}"{{ file | replace(from=root, to='$ROOT') }}" {% if not loop.last %}\
     {% endif %}{% endfor %}
-{% endfor %}
+{% endif %}{% endfor %}
 {% else %}{# compilation_mode == 'common' #}{% for file in all_verilog %}{% if loop.first %}{{ vlogan_bin }} -sverilog \
     -full64 \
     {% for tmp_arg in vlogan_args %}{{ tmp_arg }} \

src/script_fmt/vsim_tcl.tera

@@ -1,7 +1,7 @@
 # {{ HEADER_AUTOGEN }}
 set ROOT "{{ root }}"
 {% if compilation_mode == 'separate' %}{#                                                                       Individual block for each source file group
-#}{% for group in srcs %}
+#}{% for group in srcs %}{% if group.file_type != '' %}{#                                                       Only compile groups with a file type #}
 {% if source_annotations %}# {{ group.metadata }}{#                                                             Add metadata #}
 {% endif %}{% if abort_on_error %}if {[catch { {% endif %}{#                                                    Catch errors immediately
 #}{% if group.file_type == 'verilog' %}vlog -incr -sv \{#                                                       Compile verilog (& systemverilog) files with vlog -sv #}
@@ -19,7 +19,7 @@ set ROOT "{{ root }}"
     {% endif %}{% endfor %}{#                                                                                   Add group's files
 #}{% if abort_on_error %}\
 }]} {return 1}{% endif %}
-{% endfor %}{#
+{% endif %}{% endfor %}{#
 #}{% else %}{# compilation_mode == 'common' #}{#                                                                Common block for all files
 #}{% for file in all_verilog %}{% if loop.first %}{#                                                            Loop over verilog files
 #}{% if abort_on_error %}if {[catch { {% endif %}{#                                                             Catch errors immediately