feat: rv64 alu lt shift#2461
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jonathanpwang
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Mar 3, 2026
Towards INT-6319. Summary: - `branch_eq` and `branch_lt` submodules of `riscv` have been ported from RV32 to RV64 - All types/structs renamed from `Rv32*` to `Rv64*` (e.g., `Rv32BranchAdapterAir` → `Rv64BranchAdapterAir`) - Operand width changed from `u32`/4 bytes to `u64`/8 bytes throughout (registers, comparisons) - `Rv64BranchAdapter` (shared by `branch_eq` and `branch_lt`) updated for RV64 - Uncommented `branch_eq` and `branch_lt` in `extension/mod.rs` and `lib.rs` (previously marked `TEMP: disabled until ported to RV64`) - Updated tests to use RV64 conventions (8-byte arrays, `RV64_REGISTER_NUM_LIMBS`, `RV64_CELL_BITS`) --------- Co-authored-by: Claude Opus 4.6 <noreply@anthropic.com>
shuklaayush
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Towards INT-6319. Summary: - `base_alu`, `less_than`, and `shift` submodules of `riscv` have been ported from RV32 to RV64 - All types/structs renamed from `Rv32*` to `Rv64*` (e.g., `Rv32BaseAluAdapterAir` → `Rv64BaseAluAdapterAir`) - Operand width changed from `u32`/4 bytes to `u64`/8 bytes throughout (registers, ALU ops, compose/decompose helpers) - `Rv64BaseAluAdapter` (shared by all three submodules) updated for RV64 - New constraints added to enforce bytes 3–7 all equal the sign byte for correct 64-bit sign extension (previously only byte 3 was constrained for 32-bit) - Added tests for the above constraint in `base_alu`, `less_than`, `shift`. - Changed constant `DEFAULT_U8_BLOCK_SIZE` from 4 to 8 (matching RV64 register width) - Commented out unported code in `extension/mod.rs` and `lib.rs` (load/store, branch, jal/jalr, auipc, mul/div — all marked `TEMP: disabled until ported to RV64`) with manual empty-enum trait impls to keep the crate compiling - Updated `test_utils.rs` to use RV64 conventions (`generate_rv64_is_type_immediate`, `rv64_rand_write_register_or_imm`) --------- Co-authored-by: Claude Opus 4.6 <noreply@anthropic.com>
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Towards INT-6319.
Summary:
base_alu,less_than, andshiftsubmodules ofriscvhave been ported from RV32 to RV64Rv32*toRv64*(e.g.,Rv32BaseAluAdapterAir→Rv64BaseAluAdapterAir)u32/4 bytes tou64/8 bytes throughout (registers, ALU ops, compose/decompose helpers)Rv64BaseAluAdapter(shared by all three submodules) updated for RV64base_alu,less_than,shift.DEFAULT_U8_BLOCK_SIZEfrom 4 to 8 (matching RV64 register width)extension/mod.rsandlib.rs(load/store, branch, jal/jalr, auipc, mul/div — all markedTEMP: disabled until ported to RV64) with manual empty-enum trait impls to keep the crate compilingtest_utils.rsto use RV64 conventions (generate_rv64_is_type_immediate,rv64_rand_write_register_or_imm)