[CPU][ARM] Int8 conv swish fq fusion

[Passavee-Losripat]

Details:

• Re-enable ConvolutionTransformation on ARM by removing CPU_DISABLE_PASS_ARM in transformation_pipeline.cpp
• Extend ConvMulAddFQBlock pattern matcher to optionally match an activation node between Add and FakeQuantize, enabling recognition of Conv -> Mul -> Add -> Activation -> FQ in addition to the existing Conv -> Mul -> Add -> FQ. Currently supports Swish and Relu via wrap_type<Swish, Relu>
  • designed to handle for other activation in addition to Swish support in the future without structural changes
• Update ConvertConvolutionBias and FallbackUnsupportedLPConvToFP16 to retrieve and handle the optional activation anchor without breaking existing patterns
• Improve ACLConvolutionExecutor to accept Activation + FakeQuantize as simultaneous post-ops, replacing the hard single-post-op limit with an iteration loop
• Extend canFuse() in conv.cpp to allow FakeQuantize fusion after a single Eltwise activation is already fused, enabling the full post-op chain to reach the ACL executor
• Introduce isI8DstF32 / isU8DstF32 flags and use_direct_i8_s8_f32 / use_direct_u8_u8_f32 paths in ACLConvolutionExecutor so Conv can output F32 directly, letting the activation run in floating point before FQ requantizes
• Add subgraph tests covering static/dynamic shapes, per-channel and per-tensor weight scales, i8 and u8 quantized paths, with and without Swish.

Known Issues

• Per-tensor quantization (i8 and u8) fails numerically and it's under investigation. - Per-channel quantization passes.

Tickets:

• This PR is related to GSoC2026 Project 5 Optimize Quantized Model Inference Performance on ARM Devices with OpenVINO

AI Assistance:

• AI assistance used: yes
• Claude was used for writing external analyzing script and explaining codebase. All code in this PR was manually written and validated through YOLO26 detection accuracy on Apple M4 Max (ARM64). Analysis artifacts are not included in this PR.

[alvoron]

LGTM
Please fix CI pipelines and rollback ComputeLibrary submodule changes
Do we need to merge the PR as soon as we migrate to ACL with ARM-software/ComputeLibrary#1302 ?

[Passavee-Losripat]

Do we need to merge the PR as soon as we migrate to ACL with ARM-software/ComputeLibrary#1302 ?

Thank you for you review! No, the new ACL behavior only rejects the unsupported combination inside the new i8/i8/f32 path so it won't affect the existing code. Our OpenVINO code would also use fallback path until we later updates to an ACL version containing ACL#1302 as well so each PR could be updated before or after each other.

[v-Golubev]

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