cores: add SpaceMiT X60 and SiFive U74 ISA & codegen notes#29
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Add reference docs for two RISC-V cores used across the benchmark suite: - cores/x60: SpaceMiT X60 (K1) — rv64imafdcv + 30 exts, RVV 1.0 ratified VLEN=256; documents why GCC 14 has no native detection and the exact EESSI -march that matches the kernel ISA. - cores/u74: SiFive U74 (JH7110) — scalar rv64gc, no vector; in-order dual-issue single-FP-pipe tuning flags (-mtune=sifive-u74). Grounded in measured board evidence (Orange Pi RV2, VisionFive 2).
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Adds reference documentation for two RISC-V cores used across the benchmark suite.
What
cores/x60/— SpaceMiT X60 (K1) ISA & codegen notesrv64imafdcv+ 30 extensions; RVV 1.0 ratified, VLEN=256 (not 0.7.1 draft)-mcpu=native,-march=native,-mcpu=spacemit-x60all fail) and the exact EESSI-marchstring that matches the kernel-reported ISAcores/u74/— SiFive U74 (JH7110) ISA & codegen notesrv64gc, no vector unit; in-order dual-issue, single FP pipe-mtune=sifive-u74); asm microkernels stay purerv64gcWhy
Both cores are referenced repeatedly across the suite (EESSI builds, IME/RVV work, GROMACS/BLIS/HPL). These notes consolidate the ISA/codegen facts so per-benchmark docs can link to a single source of truth.
Evidence
Grounded in measured board evidence (kernel ISA strings, compiler probes) on Orange Pi RV2 and VisionFive 2. Cross-links to existing
ime/andonnx/directories.Two new files, docs-only, no code or build changes.