[jewbetcha]

What does this PR do?

Adds a DIY Layout Creator project for the second (plate R) carrier. It is generated by the same script, on the same board layout as the first:

• hardware/carrier-stripboard-right.diy (new): R1, R2, R3, R4 at the same breakout positions as L1–L4. The CS labels read CS <- D7 / D8 / D9 / A2. There is no DRDY wire (strip H notes "DRDY not wired on plate R"). The inset drops the "L1 only: DRDY" wire.
  • BUS IN wires are labelled GND / 3V3 / SCLK / MOSI / MISO, captioned "BUS IN from plate L BUS OUT". BUS OUT has no wires, and its strips say "BUS OUT empty".
  • The notes list the wires to the Q: only the 4 CS wires, A2 not D10, no DRDY. They also give the five chain wires strip to strip.
• hardware/carrier-stripboard.diy (plate L): same layout. The bus strips now read "BUS OUT -> plate R BUS IN". The notes list everything that goes to the Q (5 bus wires, CS D3–D6, L1 DRDY → D2) and point to the right-plate file.
• docs/img/make_carrier_diylc.py: build(plate) with a modules(plate) helper; __main__ writes both files.
• docs/harness.md §2: links both projects and spells out how the plate R carrier's BUS IN chains from plate L's BUS OUT.

Why was this required?

The second carrier is nearly built: the same board as the first, but with different BUS IN/OUT wiring and different connections to the Q. The repo only had the plate L project, plus a one-line note that the right one is "the same board". Plate R differs in exactly the places that are easy to get wrong: where BUS IN comes from, BUS OUT left empty, A2 rather than D10, and no DRDY.

Automated tests

None added. This changes a docs generator and its output, not code covered by tests/ (the "Tests included" check only covers app/python/open_fp and tools/sim|bench). Checked instead:

• ruff check docs/img: clean.
• Both .diy files parse as XML.
• Diffed the two generated projects. They differ only in unit names, CS pins, the DRDY wire and label, the BUS OUT wires, and the bus and notes text. Cuts, links, breakouts and cable pads are identical.

Manual (human) testing

• Regenerated both files with docs/img/make_carrier_diylc.py. The plate L file's diff is text only: the five bus-strip labels and the notes. No component positions moved.
• Opened hardware/carrier-stripboard-right.diy in DIYLC on macOS for the owner to look over against the half-built second carrier. Owner: please check it there before merging.

Checklist

• Single feature/fix — this PR is scoped to one thing with a clear story above
• Automated tests included — n/a: docs generator only (see above)
• Manual testing described — I documented what I verified by hand above
• Python tests pass (pytest)
• Ruff passes (ruff check app/python tools tests docs/img)
• Pylint passes (PYTHONPATH=app/python:tools/sim:tools/bench pylint app/python/open_fp tools/sim tools/bench --fail-under=9) — untouched paths
• Hardware changes recorded in docs/VERIFIED.md (measurements, fit checks, pin changes) — n/a, no measurement yet
• Generated files regenerated and committed (e.g. docs/img/corner-assembly.svg, CAD STL/STEP)
• Updated docs if needed
• No unrelated changes mixed in

🤖 Generated with Claude Code