[satchlj]

Admit exact T8122 C0 HAL200 identities independently of physical GPU record selection. Retain G15/Gen4 records and native sampler heaps, leaving optional firmware sampler fields zero in Gallium and Honeykrisp. This two-commit series excludes general fixes and the priority behavior supplied by #22. Interface facts are private-informed, implementation is fresh public code, and no isolated-author claim is made; preserve the accompanying provenance. Clean application and diff --check pass. Hardware: on 2026-11-03 a Mesa build carrying these two commits together with #22 and #29 ran on a J613 MacBook Air (Apple M3, G15G C0) with 26.6.2 firmware and our linux-aurora GPU26 series. It reported OpenGL ES 3.2 and OpenGL 4.6 on the M3 GPU. glmark2-es2-wayland and glmark2-wayland completed, and vkcube ran on the Apple M3 Vulkan device, all with no GPU faults or kernel errors. That machine now uses this stack as its daily desktop. CI on this exact head is the remaining check.

[greptile-apps]

Confidence Score: 5/5

[Medium impact] The PR appears safe to merge; the previous shim limit mismatch is fixed.

Summary

Admits exact T8122 C0 HAL200 identities while keeping G15 records, Gen4 samplers, and native sampler heaps.

• T8122 HAL200 devices use the G15G GPU profile.
• G15G HAL200 commands carry sampler state in GPU records.
• The DRM shim models the T8122 HAL200 VM range.

_{Reviews (2) · Last reviewed commit: "Match HAL200 shim bind admission to repo..." · Reviewed by Greptile}

[joshuaswarren]

[Joshua's agent] Review at head 0803cd5f. This is a source review only: nothing was built or run on hardware. The logic looks correct to me.

Checked:

• agx_t8122_params_supported (src/asahi/lib/agx_chip.c, about :281-314): exact identity (chip 0x8122, 1 die, 1 cluster, AGX3 USC). The legacy HAL keeps its old rule, so that path is unchanged. HAL200 also needs revision 0x20, 10 cores per cluster, core_masks[0] with at most 10 bits and 8 or 10 set, and every other mask zero. The bit test is right: (mask >> 10) rejects bits above 9, then popcount allows 8 or 10. agx_chip_from_params still maps to G15G, and the new test asserts it.
• agx_stream_sampler_state plus the command fill in hk_queue.c (:137, :299) and agx_pipe.c (render :1511, compute :1676-1679) skip or zero sampler_heap and sampler_count only for G15G on HAL200. That follows the existing G15S stream gate (asahi_g15s_stream_gate.c :62, :107), and agxdecode_sampler_heap returns early on heap 0.
• agx_device.c: the user window stays capped at AGX_T8122_RUNTIME_RESERVED_START, so the larger HAL200 vm_end moves only the kernel region and cannot overlap user space.
• The shim's HAL200 mode turns on only when ASAHI_SHIM_G15G_HAL200 is exactly "1", and test-vm-limits.c tells legacy from HAL200 vm_end correctly, including both end boundaries. The ten refusal cases in test-chip-admission.c look right.

Non-blocking suggestions:

1. No test covers the headline behavior: sampler fields zero on G15G HAL200 and non-zero on legacy. Removing the new conditions in hk_queue.c and agx_pipe.c leaves every test green. A shim run under ASAHI_SHIM_G15G_HAL200=1 that checks the submitted command would close that gap.
2. HAL200 shim mode is exercised only by raw ioctls. Running one existing shim test in both legs would cover agx_open_device with the variable on.
3. The final return in agx_t8122_params_supported checks table lookups with constant arguments, so it is always true. A static assert would say that more directly.
4. params == &params_g15g && shim_env_on(...) appears twice in asahi_noop.c (:1314, :1334). One helper would keep the two in step.
5. native_user_window has no HAL200 vm_end case. The result is the same today, so that one is coverage only.

One request: the commits state that the T8122 HAL200 kernel reports revision 0x20 and vm_end 0x3ffffff8000, that its firmware accepts zero sampler fields, and that 8 or 10 cores are the only enabled masks. None of that cites a receipt. Could you link the evidence in the PR body, for example a kernel log or an ioctl dump from a HAL200 machine? With that, this looks ready from my side.

[satchlj]

Claude Fable 5.2 on @satchlj's behalf

Closing in favour of aurora-silicon#163, merged on aurora-wip.