Merge Aurora Mesa aurora-wip: G17P submit, refit and leaf-pairing work

SILICONFOREST-SOURCES.json

@@ -2862,7 +2862,7 @@
     "aurora_merge": "5323fb87815718ca294ebe3c4f92b56cc18c577e",
     "scott_merge": "44fe9cab321168c782babaeb0f035088b574d823",
     "kernel_repository": "https://github.com/omacom/linux-aurora",
-    "kernel_commit": "7b969982306e1498a8cbe6e5da9bde743acd8fc5",
+    "kernel_commit": "6c66b41af3e77c0509ce24f3615c1bc2016cea14",
     "kernel_header": "include/uapi/drm/asahi_drm.h",
     "hardware_qualified": false,
     "system_install_performed": false

include/drm-uapi/asahi_drm.h

@@ -211,6 +211,20 @@ struct drm_asahi_params_global {
 	 * DRM_ASAHI_GPU_HAL_300 for G17G/G17S/G17C.
 	 */
 	__u32 gpu_hal_generation;
+
+	/**
+	 * @memory_limit: Device-wide limit on user committed plus kernel
+	 * resident bytes. Zero means no driver limit. This is a capacity,
+	 * not current free memory; other clients share it.
+	 */
+	__u64 memory_limit;
+
+	/**
+	 * @client_memory_limit: Per-DRM-file limit on user committed bytes.
+	 * Zero means no driver limit. Userspace must zero-initialize the reply
+	 * buffer: older kernels leave these optional tail fields untouched.
+	 */
+	__u64 client_memory_limit;
 };
 
 /**
@@ -304,6 +318,47 @@ enum drm_asahi_feature {
 	 * DRM_ASAHI_COMPUTE_AS_BUILD for a bounded long execution allowance.
 	 */
 	DRM_ASAHI_FEATURE_BOUNDED_AS_BUILD = (1UL) << 16,
+
+	/*
+	 * Bits 17 to 28 are reported only by the M5 (G17G/G17S) runtime. They
+	 * follow the numbering above, so one userspace reads every kernel's
+	 * features the same way. Bits 25 and 27 are reserved for that runtime.
+	 */
+
+	/** @DRM_ASAHI_FEATURE_RENDER_RESOURCES: Per-program render storage declarations. */
+	DRM_ASAHI_FEATURE_RENDER_RESOURCES = (1UL) << 17,
+	/** @DRM_ASAHI_FEATURE_RENDER_RESOURCES_V2: Versioned SCS and mesh storage. */
+	DRM_ASAHI_FEATURE_RENDER_RESOURCES_V2 = (1UL) << 18,
+	/** @DRM_ASAHI_FEATURE_SPARSE_TILES: DRM_ASAHI_BIND_SPARSE_TILE accepted. */
+	DRM_ASAHI_FEATURE_SPARSE_TILES = (1UL) << 19,
+	/** @DRM_ASAHI_FEATURE_COMPUTE_MATRIX: Native compute matrix instructions. */
+	DRM_ASAHI_FEATURE_COMPUTE_MATRIX = (1UL) << 20,
+	/*
+	 * Render programs accept DRM_ASAHI_RENDER_PROGRAM_TASK; task kicks get the
+	 * TA mesh rendering buffer that backs the object payload address.
+	 */
+	DRM_ASAHI_FEATURE_TASK_MESH_STORAGE = (1UL) << 21,
+	/** @DRM_ASAHI_FEATURE_RENDER_SHADER_WRITES: Per-render external shader writes. */
+	DRM_ASAHI_FEATURE_RENDER_SHADER_WRITES = (1UL) << 22,
+	/** @DRM_ASAHI_FEATURE_M5_DEPTH_MSAA_COMPRESSION: D32 2x/4x compressed depth and copy admission. */
+	DRM_ASAHI_FEATURE_M5_DEPTH_MSAA_COMPRESSION = (1UL) << 23,
+	/**
+	 * @DRM_ASAHI_FEATURE_COMPUTE_STAGE_BARRIERS: A render may carry a
+	 * separate compute prefix for its tiling half
+	 * (DRM_ASAHI_RENDER_COMPUTE_STAGE_BARRIERS,
+	 * struct drm_asahi_cmd_render_with_stage_prior).
+	 */
+	DRM_ASAHI_FEATURE_COMPUTE_STAGE_BARRIERS = (1UL) << 24,
+	/** @DRM_ASAHI_FEATURE_M5_STENCIL_MSAA_COMPRESSION: single-layer 2x/4x compressed stencil in the native ZLS form. */
+	DRM_ASAHI_FEATURE_M5_STENCIL_MSAA_COMPRESSION = (1UL) << 26,
+	/** @DRM_ASAHI_FEATURE_COMPUTE_RESOURCES: Per-dispatch storage declarations. */
+	DRM_ASAHI_FEATURE_COMPUTE_RESOURCES = (1UL) << 28,
+	/**
+	 * @DRM_ASAHI_FEATURE_CUMULATIVE_SIGNALS: SUBMIT accepts one
+	 * DRM_ASAHI_SYNC_TIMELINE_SYNCOBJ_CUMULATIVE output. All outputs
+	 * include the earlier points of that timeline without adding GPU waits.
+	 */
+	DRM_ASAHI_FEATURE_CUMULATIVE_SIGNALS = (1UL) << 29,
 };
 
 #define DRM_ASAHI_PARAM_GROUP_VM_STATUS 1
@@ -546,6 +601,15 @@ enum drm_asahi_bind_flags {
 	 * It is intended as a mechanism to accelerate sparse.
 	 */
 	DRM_ASAHI_BIND_SINGLE_PAGE = (1L << 3),
+
+	/**
+	 * @DRM_ASAHI_BIND_SPARSE_TILE: With DRM_ASAHI_BIND_SINGLE_PAGE, fill
+	 * the range from kernel-owned, physically contiguous tiles instead of
+	 * repeating the BO's first page: read-only binds read zeroes, writable
+	 * binds target a sink; both tile pools are private to the VM. The BO
+	 * only anchors the mapping. Requires DRM_ASAHI_FEATURE_SPARSE_TILES.
+	 */
+	DRM_ASAHI_BIND_SPARSE_TILE = (1L << 4),
 };
 
 /**
@@ -707,6 +771,18 @@ enum drm_asahi_cmd_type {
 	 * Followed by (possibly multiple) @drm_asahi_attachment payloads.
 	 */
 	DRM_ASAHI_SET_COMPUTE_ATTACHMENTS = 4,
+
+	/**
+	 * @DRM_ASAHI_SET_RENDER_RESOURCES: Replace linked render program storage.
+	 * Followed by zero or more drm_asahi_render_program entries. This software
+	 * command has no barriers and does not advance either command index.
+	 */
+	DRM_ASAHI_SET_RENDER_RESOURCES = 5,
+
+	/** @DRM_ASAHI_SET_COMPUTE_RESOURCES: Replace compute storage declarations. */
+	DRM_ASAHI_SET_COMPUTE_RESOURCES = 6,
+	/** Replace the render list with drm_asahi_render_program_v2 entries. */
+	DRM_ASAHI_SET_RENDER_RESOURCES_V2 = 7,
 };
 
 /**
@@ -794,6 +870,16 @@ enum drm_asahi_sync_type {
 
 	/** @DRM_ASAHI_SYNC_TIMELINE_SYNCOBJ: Timeline sync object */
 	DRM_ASAHI_SYNC_TIMELINE_SYNCOBJ = 1,
+
+	/**
+	 * @DRM_ASAHI_SYNC_TIMELINE_SYNCOBJ_CUMULATIVE: Output-only queue
+	 * timeline anchor, requiring CUMULATIVE_SIGNALS and a nonzero point.
+	 * At most one is allowed. All outputs receive completion of this submit
+	 * and the earlier anchor points.
+	 * Other outputs must not alias the anchor. No execution dependency is
+	 * added. Calls updating this private anchor must be externally serialized.
+	 */
+	DRM_ASAHI_SYNC_TIMELINE_SYNCOBJ_CUMULATIVE = 2,
 };
 
 /**
@@ -819,6 +905,87 @@ struct drm_asahi_sync {
  */
 #define DRM_ASAHI_BARRIER_NONE (0xFFFFu)
 
+/**
+ * struct drm_asahi_compute_program - Storage of one linked compute dispatch.
+ *
+ * SET_COMPUTE_RESOURCES replaces the list for subsequent compute commands.
+ * Include each distinct dispatch profile in the command stream. The kernel
+ * combines their requirements before publishing work. All sizes are bytes.
+ */
+struct drm_asahi_compute_program {
+	/** @primary_bytes: Per-thread primary storage. */
+	__u32 primary_bytes;
+	/** @secondary_bytes: Per-thread secondary storage. */
+	__u32 secondary_bytes;
+	/** @linked_bytes: Additional primary storage after linking. */
+	__u32 linked_bytes;
+	/** @minimum_primary_bytes: Minimum primary storage across variants. */
+	__u32 minimum_primary_bytes;
+	/** @threadgroup_bytes: Storage shared by a workgroup. */
+	__u32 threadgroup_bytes;
+	/** @threads: Number of invocations in a workgroup. */
+	__u32 threads;
+	/** @flags: Reserved; must be zero. */
+	__u32 flags;
+};
+
+/**
+ * struct drm_asahi_render_program - Storage of one linked render program.
+ *
+ * SET_RENDER_RESOURCES replaces the list for subsequent renders in this submit.
+ * Include every vertex and fragment program, including background and end-of-tile
+ * programs. Sizes describe the final linked program, in bytes. Each entry is
+ * evaluated separately before taking the maximum demand across the pass.
+ */
+struct drm_asahi_render_program {
+	/** @stage: 0 for vertex, 1 for fragment (including background/end-of-tile). */
+	__u32 stage;
+	/** @primary_bytes: Primary per-thread storage after linking. */
+	__u32 primary_bytes;
+	/** @secondary_bytes: Secondary per-thread storage after linking. */
+	__u32 secondary_bytes;
+	/** @linked_bytes: Additional primary storage from linked programs. */
+	__u32 linked_bytes;
+	/** @minimum_primary_bytes: Minimum primary storage across linked variants. */
+	__u32 minimum_primary_bytes;
+	/** @auxiliary_count: Fragment auxiliary entries; zero for vertex programs. */
+	__u32 auxiliary_count;
+	/** @threadgroup_bytes: Fragment threadgroup storage; zero for vertex. */
+	__u32 threadgroup_bytes;
+	/** @imageblock_bytes: Fragment imageblock storage; zero for vertex. */
+	__u32 imageblock_bytes;
+	/** @multisample_bytes: Fragment multisample storage; zero for vertex. */
+	__u32 multisample_bytes;
+	/** @flags: MBZ. */
+	__u32 flags;
+};
+/** Version 2 linked render storage. Version 1 remains exactly 40 bytes. */
+#define DRM_ASAHI_RENDER_PROGRAM_SCS (1U << 0)
+#define DRM_ASAHI_RENDER_PROGRAM_MESH (1U << 1)
+#define DRM_ASAHI_RENDER_PROGRAM_OBJECT (1U << 2)
+/* With OBJECT: the object program is an API task stage. The kernel binds the
+ * TA mesh rendering buffer (the backing of the object payload address) to
+ * such kicks only. Requires DRM_ASAHI_FEATURE_TASK_MESH_STORAGE. */
+#define DRM_ASAHI_RENDER_PROGRAM_TASK (1U << 3)
+struct drm_asahi_render_program_v2 {
+	struct drm_asahi_render_program legacy;
+	/** @threads: Mesh/object workgroup invocation count; zero otherwise. */
+	__u32 threads;
+	/** @usage_flags: DRM_ASAHI_RENDER_PROGRAM_* bits. */
+	__u32 usage_flags;
+	/** @scs_layout: Packed depth/levels/cliques/user/driver SCS layout. */
+	__u64 scs_layout;
+	/** @auxiliary_allocation: Stage native auxiliary allocation word. */
+	__u32 auxiliary_allocation;
+	__u32 reserved;
+	__u64 intersection_pool;
+	__u64 intersection_pool_bytes;
+	__u32 intersection_first;
+	__u32 intersection_count;
+	__u64 intersection_default_program;
+	__u64 intersection_default_control;
+};
+
 /**
  * struct drm_asahi_cmd_header - Top level command structure
  *
@@ -1032,6 +1199,24 @@ enum drm_asahi_render_flags {
 	 * may depend on it. Requires DRM_ASAHI_FEATURE_FRAGMENT_BARRIERS.
 	 */
 	DRM_ASAHI_RENDER_FRAGMENT_BARRIERS = (1U << 20),
+
+	/**
+	 * @DRM_ASAHI_RENDER_SHADER_WRITES: A graphics program in this command
+	 * writes external memory, including buffer/image stores or atomic RMW.
+	 * Ordinary raster outputs and compiler-private transport do not count.
+	 * Requires DRM_ASAHI_FEATURE_RENDER_SHADER_WRITES. Omission retains the
+	 * existing encoding, allowing older userspace to submit unchanged.
+	 */
+	DRM_ASAHI_RENDER_SHADER_WRITES = (1U << 21),
+
+	/**
+	 * @DRM_ASAHI_RENDER_COMPUTE_STAGE_BARRIERS: The command is a struct
+	 * drm_asahi_cmd_render_with_stage_prior. Its tiling half waits only on
+	 * the compute prefix named by ta_cdm_barrier and ta_prior_cdm, which must
+	 * not exceed the command's own compute prefix; its fragment half waits on
+	 * the whole one. Requires DRM_ASAHI_FEATURE_COMPUTE_STAGE_BARRIERS.
+	 */
+	DRM_ASAHI_RENDER_COMPUTE_STAGE_BARRIERS = (1U << 22),
 };
 
 /**
@@ -1370,6 +1555,19 @@ struct drm_asahi_cmd_render_with_prior {
 	__u64 prior_cdm;
 };
 
+/* DRM_ASAHI_RENDER_COMPUTE_STAGE_BARRIERS: the tiling half's compute prefix,
+ * a command index like drm_asahi_cmd_header::cdm_barrier and an exact prior
+ * ordinal like prior_cdm. Its tail takes the place of the ray-query stage
+ * state of struct drm_asahi_cmd_render_with_ray_query, so a command carries
+ * one of the two. */
+struct drm_asahi_cmd_render_with_stage_prior {
+	struct drm_asahi_cmd_render_with_prior legacy;
+	__u16 ta_cdm_barrier;
+	__u16 reserved0;
+	__u32 reserved1;
+	__u64 ta_prior_cdm;
+};
+
 struct drm_asahi_render_ray_query_stage {
 	__u64 scs_layout;
 	__u32 intersection_aux;
@@ -1444,13 +1642,30 @@ struct drm_asahi_cmd_compute_with_prior {
 	__u64 scs_layout;
 	__u64 prior_vdm;
 	__u64 prior_cdm;
+	/* Native M5 compute allocation word, independent of scs_layout.
+	 * Zero preserves the legacy path. Older kernels reject a nonzero tail. */
 	__u32 cdm_auxiliary_allocation;
 	__u32 reserved;
+	/** @intersection_pool: M5 intersection-table pool, 16 KiB aligned. */
 	__u64 intersection_pool;
+	/** @intersection_pool_bytes: Mapped size, a multiple of 16 KiB. */
 	__u64 intersection_pool_bytes;
+	/** @intersection_first: First 128-byte driver table block. */
 	__u32 intersection_first;
+	/** @intersection_count: Number of driver table blocks (1..262143). */
 	__u32 intersection_count;
+	/**
+	 * @intersection_default_program: Native default program descriptor.
+	 * Low 48 bits are the 64-byte aligned program address; upper 16 bits
+	 * contain the low resource-specification bits.
+	 */
 	__u64 intersection_default_program;
+	/**
+	 * @intersection_default_control: Native default program control word.
+	 * Bits 13:0 and 46:32 are defined by the M5 program descriptor. All
+	 * other bits must be zero. A nonzero default program requires bit 40.
+	 * An all-zero intersection extension preserves the ordinary compute path.
+	 */
 	__u64 intersection_default_control;
 };
 
@@ -1473,6 +1688,16 @@ enum drm_asahi_compute_flags {
 	 * ordered helpers cannot time out while waiting for the build.
 	 */
 	DRM_ASAHI_COMPUTE_AS_BUILD = (1L << 2),
+
+	/*
+	 * Bits 16 and up are accepted only by the M5 (G17G/G17S) runtime.
+	 */
+
+	/**
+	 * @DRM_ASAHI_COMPUTE_USES_MATRIX: The command's dispatches use native
+	 * matrix instructions. Requires DRM_ASAHI_FEATURE_COMPUTE_MATRIX.
+	 */
+	DRM_ASAHI_COMPUTE_USES_MATRIX = (1L << 16),
 };
 
 /**