Restore M3 Pro Vulkan capabilities and fix the Clang test build

OMACOM-M3PRO-20261026.json

@@ -0,0 +1,101 @@
+{
+  "schema": 1,
+  "recorded_utc": "2026-10-26T10:44:41.216352+00:00",
+  "model": "J514S, Apple M3 Pro (G15S B1)",
+  "source_repository": "https://github.com/omacom/mesa",
+  "integration_base": "7c86130d26cecd50c7af1ac01ff3fa1705d58045",
+  "tested_source": "eaf69705c33249bd5e4f4ac2211bdcc6fad94f63",
+  "tested_tree": "4ef9418d79cd92a353c5beae0d9dcd89d6efb167",
+  "kernel": "7.2.11-m3plasma-16575aa-ARCH",
+  "kernel_source": "16575aa9c769e9bede0ab58dc26f9d91dc07182f",
+  "kernel_prs": [
+    "https://github.com/omacom/linux-aurora/pull/233",
+    "https://github.com/omacom/linux-aurora/pull/238"
+  ],
+  "package": "mesa-m3-pro-g15 26.3.0.omacom.eaf69705c3-1",
+  "package_sha256": "cad98edb9dcd296a6b6ba0eaecaf21771b1a912b2020446b61c817eebabef626",
+  "assertions_enabled": true,
+  "library_sha256": {
+    "opt/mesa-m3-pro-g15/lib/libvulkan_asahi.so": "22e5b5686b4d3e78c4a5c851a664683138fd895db814abf3e9a65b40d49e7ab5",
+    "opt/mesa-m3-pro-g15/lib/libasahi_noop_drm_shim.so": "5bf327deba3274d992ee20b92aff9271be09ad404178b2362a4240e1ea36afa2",
+    "opt/mesa-m3-pro-g15/lib/libgallium-26.3.0-devel.so": "8c739a31738042ff614fbacaba27e37317aa8b3859c16c872f4334595a04010d",
+    "opt/mesa-m3-pro-g15/lib/libGLX_mesa.so.0.0.0": "11cd754595287d5d6e49810502f2bcea06e3af41ab75307bb4ef8623968dbf20",
+    "opt/mesa-m3-pro-g15/lib/libgbm.so.1.0.0": "800a853315840ff5045666e2eccb5a52427abe7e6d39a65672d6c88101e01213",
+    "opt/mesa-m3-pro-g15/lib/libEGL_mesa.so.0.0.0": "6e00b003acbecef3cf577bea4fc663fd63180d0e3aa34c752ea4d30915400b6f"
+  },
+  "validation": {
+    "host_meson_suites": 139,
+    "host_failures": 0,
+    "production_cpu_programs": 5,
+    "shim_profiles": "G13G/G15S/G15C/G17P/G15G admitted; Air obsolete opt-in 0/1 unchanged; G16G refused; zero validation errors, no submits",
+    "red_before_fix": "G15S maxBoundDescriptorSets assertion fails at source 25fe0160a0",
+    "fresh_boot": true,
+    "kwin_uses_packaged_libraries": true,
+    "gl_readback": {
+      "frames": 64,
+      "incorrect_channels": 0
+    },
+    "vk_descriptor_sets": {
+      "indices": [
+        0,
+        7,
+        8,
+        15
+      ],
+      "dispatches_each": 8,
+      "words_each": 524288,
+      "incorrect_words": 0,
+      "validation_errors": 0
+    },
+    "cts": {
+      "reported": {
+        "Pass": 6,
+        "Flake": 1
+      },
+      "focused": {
+        "Pass": 561,
+        "Warn": 4,
+        "Skip": 5
+      },
+      "wider": {
+        "Pass": 7054,
+        "Skip": 5198
+      },
+      "capabilities": {
+        "Pass": 359,
+        "Skip": 1670
+      },
+      "sets16": {
+        "Pass": 2694,
+        "Skip": 4320
+      }
+    },
+    "wider_results_identical_to_previous_installed_mesa": true,
+    "plasma_settings_launches": 10,
+    "plasma_light_dark_cycles": 10,
+    "kwin_pid_unchanged_during_plasma_test": true,
+    "plasma_coredumps": 0,
+    "gpu_recoveries": 0,
+    "gpu_hang_kills": 0,
+    "theme_restored_via_desktop_manager": true
+  },
+  "benchmark": {
+    "capture_seconds": 10,
+    "resolution": [
+      1920,
+      1080
+    ],
+    "before_source": "ea2c18f45c496034fd97a833c027011d1216a9b1",
+    "before_fps": 370.24039515784386,
+    "after_fps": 416.4074536934211,
+    "same_game_pak_config_kernel": true,
+    "scope": "One matched sample each across the Mesa branch upgrade and reboot; not an isolated gain from the two new patches."
+  },
+  "limitations": [
+    "Full Vulkan 1.4 CTS not rerun; the user will run it separately.",
+    "Only J514S hardware was tested; other G15 profiles were preserved.",
+    "No full OpenGL conformance run.",
+    "The reported seven-case group contains one wrong-result flake (uaddcarry.uvec3_highp_geometry): outputs remained at the clear colour, then the automatic retry passed. Similar dropped draws predate this PR; cause unresolved.",
+    "All 384 conditional-rendering draw cases and all 60 clear-attachment cases skip; these paths are not hardware-qualified by this receipt."
+  ]
+}

SILICONFOREST-REVIEW.md

@@ -185,3 +185,44 @@ the real `poly_heap` declaration. Twelve real XML-parser-to-callback checks
 covered negative, zero, in-range and oversized values, including 4096/5000 MiB;
 all allocated and published the same bounded size. Removing the clamp fails
 the maintained regression. These are host checks, without GPU qualification.
+
+## October 26 M3 Pro qualification
+
+The last local packed-GS-output and select-guard fixes are already covered
+by `d4b6840f` and `ae035d59`; no duplicate production patches are imported.
+Jonathan Goyvaerts's public `141481c` warning/build fixes are replayed with
+original attribution and `-x` provenance. They resolve Clang's enabled-test
+build failures in the command-stream header.
+
+Restore the conditional-rendering, unified-image-layouts, memory-budget and
+sixteen-set profile on hardware-tested G15S only. Other G15 profiles and the
+FMA/rounding and kernel/device admission checks retain their existing policy.
+The actual-driver shim probe rejects the previous G15S profile and verifies
+both the restored profile and the unchanged profiles.
+
+[The J514S receipt](OMACOM-M3PRO-20261026.json) pins built source `eaf69705c3`,
+Arch package/library hashes and the initial kernel. GPU readbacks through
+set 15, 139 host suites, the sixteen-set graphics/compute group and
+Settings/theme cycles pass.
+
+The seven-case regression group has six passes and one intermittent failure
+that passes retry. Geometry-shader output sometimes remains at the clear
+colour; this was also observed with the earlier Mesa and kernel. The receipt
+records a `uvec3_highp_geometry` failure; the rebased kernel `8824dd6` showed
+the same symptom in `uint_highp_geometry`. This dropped-draw defect remains
+unresolved and is not a clean pass or an established consequence of load.
+
+All 384 conditional-rendering draw cases and all 60 clear-attachment cases
+skip. Exposing conditional rendering does not qualify these skipped paths;
+the current full suite will not validate paths it also skips. Skips and
+warnings remain in the receipt. Full Vulkan 1.4 CTS on the rebased stack is
+pending the owner's run; the earlier full result belongs to a different Mesa.
+
+Newer shared-native candidates remain separate review work: bank-constrained
+RA recovery (`c7d849e5`), passthrough-GS OOM reporting (`89bb9b98`), uniform
+atomics (`52e35626`), application then internal compute DMA (`a29a074b`,
+`43901729`), and occlusion availability (`e07644ef`, `360a1c91`). The blend
+series `8fc7dc70` also touches shared native paths; its new constant-program
+fast path requires G17P's qualified preamble. None is qualified on M3 by this
+receipt. G17P-only timestamp/cache-range/signal optimizations, RT work and
+virtio-only unbind handling are not direct-DRM M3 prerequisites.

SILICONFOREST-SOURCES.json

@@ -2856,7 +2856,7 @@
       "review_hardening_commit": "db96168675f5464d5293caf48ed718792b2bed74"
     }
   ],
-  "last_integration_update": "2026-10-24",
+  "last_integration_update": "2026-10-26",
   "integration_followups_20261024": {
     "base": "7515336b3dfbe8943b555ffec9817b9ed64379a8",
     "aurora_merge": "5323fb87815718ca294ebe3c4f92b56cc18c577e",
@@ -2866,5 +2866,17 @@
     "kernel_header": "include/uapi/drm/asahi_drm.h",
     "hardware_qualified": false,
     "system_install_performed": false
+  },
+  "integration_followups_20261026": {
+    "base": "7c86130d26cecd50c7af1ac01ff3fa1705d58045",
+    "public_source_repository": "https://github.com/aurora-silicon/mesa",
+    "public_source_inspected": "f2c9dc3fb59c81fdaf51f19884175c856e3d1889",
+    "imported_commit": "141481c19964ac29dbd1707d4c99a2dfbc638999",
+    "local_import_commit": "25fe0160a04e8d56c5ed01e9892164e9ee3e7127",
+    "tested_source": "eaf69705c33249bd5e4f4ac2211bdcc6fad94f63",
+    "hardware_record": "OMACOM-M3PRO-20261026.json",
+    "hardware_scope": "J514S/G15S only; targeted checks and reboot; full CTS pending",
+    "existing_gs_fix": "d4b6840f7af8a25af48566589af41609e0871b9e",
+    "existing_select_guard_fix": "ae035d592921d018c9431c4b1810300387e7d48b"
   }
 }

src/asahi/compiler/agx3_mesh_core.c

@@ -82,7 +82,8 @@ agx3_mesh_passthrough_object(uint16_t grid_uniform, uint8_t out[64],
    const struct agx3_field_kv fields[]={__VA_ARGS__}; \
    if(!agx3_bind_compose(AGX_ISA_ENCODING_AGX3C,name,ep,fields, \
                          sizeof(fields)/sizeof(fields[0]),NULL,0,temp+n,&size)) \
-      return false; n+=size; \
+      return false; \
+   n+=size; \
 } while(0)
    EMIT("rld",1,KV(9,2),KV(10,1),KV(11,1),KV(12,1),KV(21,13),
         KV(23,7),KV(24,1),KV(28,4),KV(29,144),KV(38,1));

src/asahi/compiler/test/test-mixed-uniform-alu.cpp

@@ -131,8 +131,9 @@ TEST(MixedUniformALU, OptimizerFoldsUniformWideningOnlyIntoNativeShapes)
          agx_optimizer_forward(b->shader);
          EXPECT_EQ(I->src[1].type == AGX_INDEX_UNIFORM,
                    !uniform_other && !saturate);
-         if (!uniform_other && !saturate)
+         if (!uniform_other && !saturate) {
             EXPECT_EQ(I->src[1].size, AGX_SIZE_16);
+         }
          ralloc_free(mem);
       }
    }

src/asahi/compiler/test/test-native-form-regressions.cpp

@@ -568,8 +568,9 @@ TEST(NativeForms, PhiEdgeAffinityRespectsTileBankAndLiveValues)
       ASSERT_FALSE(b->shader->ra_failed);
       EXPECT_LT(use->src[0].value, agx3_tile_store_bank(b->shader));
       EXPECT_EQ(use->src[0].value, mode == 0 ? 10u : 1u);
-      if (held_use)
+      if (held_use) {
          EXPECT_EQ(held_use->src[0].value, 10u);
+      }
       unsigned copies = 0;
       agx_foreach_instr_global(b->shader, I)
          copies += I->op == AGX_OPCODE_MOV;
@@ -1729,10 +1730,12 @@ TEST(NativeForms, ScalarCubeAllocationPreservesSharedInputs)
             EXPECT_TRUE(I->dest[0].value + 8 <= keep->src[0].value ||
                         I->dest[0].value >= keep->src[0].value + 2);
          }
-         if (mode == 2)
+         if (mode == 2) {
             EXPECT_EQ(I->src[6].value, I->src[7].value);
-         if (mode == 0 || mode == 4)
+         }
+         if (mode == 0 || mode == 4) {
             EXPECT_EQ(I->dest[0].value, 8u);
+         }
       }
       EXPECT_EQ(samples, mode == 3 ? 2u : 1u);
       ralloc_free(mem);
@@ -2432,8 +2435,9 @@ TEST(NativeForms, TextureFmaStagingAdmission)
       const bool supported =
          invalid == 0 || invalid == 9 || invalid == 12 || invalid == 13;
       EXPECT_FALSE(sample->agx3_tex_coords_staged);
-      if (publication)
+      if (publication) {
          EXPECT_EQ(publication->agx3_tex_coords_staged, supported);
+      }
       if (supported) {
          ASSERT_NE(publication, nullptr);
          EXPECT_TRUE(first->agx3_tex_coord_start);
@@ -2516,8 +2520,9 @@ TEST(NativeForms, TextureFmaStagingPreservesDemand)
    unsigned index = 0;
    agx_foreach_instr_global(b->shader, I) {
       EXPECT_FALSE(I->agx3_tex_coords_staged);
-      if (I->op == AGX_OPCODE_FFMA)
+      if (I->op == AGX_OPCODE_FFMA) {
          EXPECT_EQ(I->dest[0].type, AGX_INDEX_NORMAL);
+      }
       if (agx_is_texture_publication(I)) {
          EXPECT_EQ(I->src[0].type, AGX_INDEX_NORMAL);
          EXPECT_EQ(I->src[1].type, AGX_INDEX_NORMAL);
@@ -2571,8 +2576,9 @@ TEST(NativeForms, MultipleTextureFmaPublications)
    unsigned stages = 0, publications = 0;
    agx_foreach_instr_global(b->shader, I) {
       stages += I->agx3_tex_coord_stage;
-      if (I->agx3_tex_coord_stage)
+      if (I->agx3_tex_coord_stage) {
          EXPECT_TRUE(agx_is_null(I->dest[0]));
+      }
       if (agx_is_texture_publication(I)) {
          publications++;
          EXPECT_TRUE(I->agx3_tex_coords_staged);
@@ -2631,8 +2637,9 @@ TEST(NativeForms, TextureFmaPublicationPrecedesEarlierSamples)
          EXPECT_TRUE(I->agx3_tex_coords_staged);
          published = true;
       }
-      if (I == samples[0])
+      if (I == samples[0]) {
          EXPECT_TRUE(published);
+      }
    }
    EXPECT_TRUE(published);
    ralloc_free(mem);
@@ -3312,8 +3319,9 @@ TEST(LegacySamplers, UnpromotedIndexNeedsHeap)
          agx_shader_part part = {};
          bool ok = agx_compile_shader_nir(b.shader, &key, &part);
          EXPECT_TRUE(ok);
-         if (ok)
+         if (ok) {
             EXPECT_TRUE(part.info.uses_sampler_heap);
+         }
          free(part.binary);
          ralloc_free(b.shader);
       }

src/asahi/compiler/test/test-optimizer.cpp

@@ -1290,8 +1290,9 @@ TEST_F(Optimizer, G17PRangeSelectImmediateBoundary)
       agx_optimize_and_dce(after->shader);
       agx_foreach_instr_global(after->shader, I) {
          agx_foreach_src(I, s) {
-            if (I->src[s].type == AGX_INDEX_IMMEDIATE)
+            if (I->src[s].type == AGX_INDEX_IMMEDIATE) {
                ASSERT_LT(I->src[s].value, 256u);
+            }
          }
       }
       for (uint32_t input : {0u, 254u, 255u, 256u, 257u, 65535u})

src/asahi/compiler/test/test-preamble-modifiers.cpp

@@ -20,8 +20,9 @@ check_modifier(bool g17p, bool widen)
    unsigned sizes[3] = {16, 0, 0};
    bool progress = agx_nir_opt_preamble(b.shader, sizes, g17p);
    const bool hoisted = g17p && !widen;
-   if (hoisted)
+   if (hoisted) {
       EXPECT_TRUE(progress);
+   }
    unsigned modifiers = 0, exported = 0;
    nir_function_impl *main = nir_shader_get_entrypoint(b.shader);
    nir_foreach_block(block, main) {
@@ -38,8 +39,9 @@ check_modifier(bool g17p, bool widen)
    }
    EXPECT_EQ(modifiers, hoisted ? 0u : 1u);
    EXPECT_EQ(exported, hoisted ? 1u : 0u);
-   if (hoisted)
+   if (hoisted) {
       EXPECT_EQ(sizes[0], 18u);
+   }
    ralloc_free(b.shader);
 }
 

src/asahi/genxml/agx3_cmdstream.h

@@ -240,7 +240,7 @@ agx3_cdm_launch_pack(const struct agx3_cdm_launch_info *info,
    struct AGX_CDM_LAUNCH_AGX3 header = {
       .word_0_payload = info->word0_payload,
       .word_1_payload = info->word1_payload,
-      .pipeline_hi = info->pipeline >> 38,
+      .pipeline_hi = (uint32_t)(info->pipeline >> 38),
       .pipeline_lo = (uint32_t)(info->pipeline >> 6),
       .opaque_word_3 = info->opaque_word3,
    };
@@ -360,7 +360,7 @@ agx3_cdm_indirect_launch_unpack(
       .pipeline = ((uint64_t)(word1 >> 22) << 38) |
                   ((uint64_t)agx3_cmdstream_load_le32(bytes + 8) << 6),
       .opaque_word3 = agx3_cmdstream_load_le32(bytes + 12),
-      .indirect_word4_payload = word4 >> 16,
+      .indirect_word4_payload = (uint16_t)(word4 >> 16),
       .indirect_parameters = ((uint64_t)(word4 & 0xffff) << 32) |
                              agx3_cmdstream_load_le32(bytes + 20),
    };
@@ -437,7 +437,7 @@ agx3_cdm_indirect_launch_36_unpack(
       .pipeline = ((uint64_t)(word1 >> 22) << 38) |
                   ((uint64_t)agx3_cmdstream_load_le32(bytes + 8) << 6),
       .opaque_word3 = agx3_cmdstream_load_le32(bytes + 12),
-      .indirect_word4_payload = word4 >> 16,
+      .indirect_word4_payload = (uint16_t)(word4 >> 16),
       .indirect_parameters = ((uint64_t)(word4 & 0xffff) << 32) |
                              agx3_cmdstream_load_le32(bytes + 20),
    };
@@ -467,7 +467,7 @@ agx3_cdm_stream_link_pack(
       return false;
 
    struct AGX_CDM_STREAM_LINK_AGX3 link = {
-      .target_hi = info->target >> 32,
+      .target_hi = (uint32_t)(info->target >> 32),
       .with_return = info->with_return,
       .target_lo = (uint32_t)info->target,
    };

src/asahi/lib/tests/test-g17p-msaa-epilog.cpp

@@ -300,8 +300,9 @@ TEST(LegacyFragments, EpilogUsesUpstreamDepthCoverage)
          if (intr->intrinsic != nir_intrinsic_store_zs_agx) continue;
          zs++;
          EXPECT_TRUE(nir_src_is_const(intr->src[0]));
-         if (nir_src_is_const(intr->src[0]))
+         if (nir_src_is_const(intr->src[0])) {
             EXPECT_EQ(nir_src_as_uint(intr->src[0]), 0xffu);
+         }
       }
    }
    EXPECT_EQ(zs, 1u);

src/asahi/vulkan/hk_acceleration_structure.c

@@ -184,7 +184,7 @@ hk_gen1_sparse_entry(struct hk_device *dev, struct hk_gen1_sparse_table *t,
       if (agx_bo_bind(&dev->dev, bo,
                       t->va->addr + (uint64_t)next * HK_GEN1_SPARSE_PAGE_BYTES,
                       HK_GEN1_SPARSE_PAGE_BYTES, 0, t->bind_flags)) {
-         util_dynarray_pop(&t->pages, struct agx_bo *);
+         (void)util_dynarray_pop_ptr(&t->pages, struct agx_bo *);
          agx_bo_unreference(&dev->dev, bo);
          return NULL;
       }

src/asahi/vulkan/hk_cmd_draw.c

@@ -3204,7 +3204,6 @@ hk_m5_ordered_draw_hazard(struct hk_cmd_buffer *cmd)
 static bool
 hk_m5_pass_merge_begin(struct hk_cmd_buffer *cmd, const VkRenderingInfo *info)
 {
-   struct hk_device *dev = hk_cmd_buffer_device(cmd);
    struct hk_pass_merge_candidate *m = &cmd->state.pass_merge;
    struct hk_cs *cs = m->cs;
    const struct hk_rendering_state *prev = &m->render;
@@ -3245,19 +3244,15 @@ hk_m5_pass_merge_begin(struct hk_cmd_buffer *cmd, const VkRenderingInfo *info)
       return false;
    }
 
-   const char *slot = NULL;
    if (!why) {
-      slot = "depth";
       why = hk_m5_attachment_continues(info->pDepthAttachment,
                                        &prev->depth_att);
    }
    if (!why) {
-      slot = "stencil";
       why = hk_m5_attachment_continues(info->pStencilAttachment,
                                        &prev->stencil_att);
    }
    for (uint32_t i = 0; !why && i < info->colorAttachmentCount; ++i) {
-      slot = "color";
       why = hk_m5_attachment_continues(&info->pColorAttachments[i],
                                        &prev->color_att[i]);
    }